1 to 25 of 40 Permanent Perl Jobs in England

Ansible, Terraform, etc.) Experience in creating automation framework using Ansible Understanding in one or two Scripting and programming languages (such as Python/Perl, Groovy, Shell Scripting, etc.) Familiarity with microservices architecture and container orchestration with Kubernetes (Ideally with EKS) Experience in defining quality gates (integrating SonarQube Static Code analysis ...

level cyber security certification (e.g. Security+, CEH, CPSA) or similar. It would be great if you had: Scripting or programming skills (Python, PowerShell, Bash, Perl, C++). Broader SIEM experience (e.g. QRadar). Additional SOC or CREST certifications. If you’re interested in this role but not sure if your ...

level cyber security certification (e.g. Security+, CEH, CPSA) or similar. It would be great if you had: Scripting or programming skills (Python, PowerShell, Bash, Perl, C++). Broader SIEM experience (e.g. QRadar). Additional SOC or CREST certifications. If you're interested in this role but not sure if your ...

software (unit and system levels). Experience in running simulations, developing and running models on a Linux Operating System and common Linux tools (BASH, PERL). Knowledge of Tactics, Techniques, and Procedures (TTPs) of EW capability within the Air domain. Knowledge of version/source control software (Git, Bitbucket). ...

/Openstack). Virtualisation platform exposure, VMware/HyperV/other Django Web Framework SQL/MySQL/VBA/Python/Java/Perl/Bash and or similar scripting language knowledge. ...

manage AWS infrastructure using Terraform and CloudFormation Provide input into cloud strategy, deployment standards, and best practices Work across a mixed tech stack ( Perl, Python, Go, TypeScript/JavaScript ) What we’re looking for Experience with AWS and cloud architecture Practical containerisation experience Hands-on Infrastructure as Code (Terraform ...

Environmental/EMC/EMI/TEMPEST testing. Competence in modelling techniques for test scoping or environment design. Scripting languages (e.g., Python, Bash, JavaScript, Perl). Knowledge of iterative and modern development methods such as TDD, BDD, ATDD. Why Join? Work on mission-critical systems with tangible national security impact. ...

number of years’ experience supporting Cadence and Siemens EDA design tools (Virtuoso, Calibre) with commercial PDKs Strong scripting skills in Python/Bash/Perl Excellent communication and analytical skills with sound judgment and practical insight A keen interest to contribute to one of the UK’s fastest growing start ...

complex SoCs. Experience with Scan/EDT, MBIST, and Boundary Scan. Experience creating iJTAG structures in Verilog. Strong debug skills using waveforms. Experience with Perl scripting for EDA flows. Interested in hearing more? Please apply ...

complex SoCs. Experience with Scan/EDT, MBIST, and Boundary Scan. Experience creating iJTAG structures in Verilog. Strong debug skills using waveforms. Experience with Perl scripting for EDA flows. Interested in hearing more? Please apply ...

functional requirements for verification environments & metrics SystemVerilog UVM testbenches Formal proof verification Understanding of C test cases and C code Scripting languages (e.g. Python, Perl, TCL) Desirable skills Experience with formal verification tools (JasperGold, VC Formal) Familiarity with C/C++ development Prior SSD experience with storage interfaces such ...

SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...

SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...

SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...

SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...

SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...

SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...

SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...

SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...

SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...

SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...

SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...

SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...

SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...

SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...