4 of 4 Permanent Senior Validation Engineer Jobs in Farnborough

Senior Validation Engineer (Systems / DDR Subsystems)

Hiring Organisation
Jobleads-UK
Location
Farnborough, England, United Kingdom
technology leader in satellite communication. This role requires a strong understanding of DDR protocols, FPGA development, system bring-up, signal integrity, and post-silicon validation . Key Responsibilities: DDR System Validation Validate DDR3/DDR4 interfaces on modem platforms Develop comprehensive DDR validation plans covering functionality, timing … tools FPGA Development& Prototyping Develop FPGA-based prototypes for modem subsystems Bring up FPGA platforms and validate hardware functionality Support hardware/software co-validation using FPGA platforms Knowledge of Verilog/SystemVerilog FPGA bring-up System-Level Validation Perform board bring-up and system integration Validate high ...

Senior SerDes & PHY Systems Validation Engineer

Hiring Organisation
Jobleads-UK
Location
Farnborough, England, United Kingdom
Space is seeking a Sr. Systems Validation Engineer (SerDes/Physical Layer) to join our Farnborough team. You will validate high‐speed SerDes PHY, perform link bring‐up, and tune equalization while coordinating with the Chip Validation Team Leader. You will develop chip and system test plans ...

Senior SerDes & PHY Systems Validation Engineer

Hiring Organisation
Jobleads-UK
Location
Farnborough, England, United Kingdom
Space in Farnborough is seeking a Sr. Systems Validation Engineer to validate high‐speed SerDes PHYs, lead lab bring‐up and tuning, and develop automated test plans for chip and system level validation. The role involves working with real‐world RF/analog test equipment, performing eye diagrams ...

Senior DDR Validation & FPGA Engineer – Space Systems

Hiring Organisation
Jobleads-UK
Location
Farnborough, England, United Kingdom
Space in Farnborough is seeking an experienced engineer to drive DDR validation, FPGA development and system bring-up for high-speed modem platforms. You will collaborate with RTL, memory controller, PHY and software teams, perform margin/eye analyses, develop automated validation scripts, and ensure production readiness ...