3 of 3 Permanent Verification Engineer Jobs in Hampshire

Senior Verification Engineer

Location
Southampton, England, United Kingdom
Senior Verification Engineer Department: Hardware Employment Type: Full Time Location: Southampton, UK Reporting To: Tom Hollis Description Our RTL team delivers efficient ASIC and FPGA implementations of advanced communications algorithms, working across IP development, integration and verification. To support this work, we are looking for a Senior Verification Engineer to support the complete UVM verification of Accelercomm IP. Purpose Responsible for verification of RTL implementations for advanced wireless communications IP and modem subsystems, ensuring designs meet functional, performance and quality requirements prior to FPGA deployment and ASIC tape-out. Key Responsibilities Develop verification ...

Design Verification Engineer

Location
Southampton, England, United Kingdom
need to scale engineering capability as products move towards high-volume deployment. As part of that growth, they're looking for a Senior Verification Engineer to take ownership of UVM-based verification across complex communications IP. Working closely with architects, RTL designers and systems engineers … involved from specification through to sign-off, developing verification plans, building SystemVerilog/UVM environments, creating coverage models and debugging issues across both RTL and verification environments. You'll likely bring SystemVerilog and UVM experience ASIC and/or FPGA verification experience Coverage-driven and assertion-based ...

Senior Verification Engineer — L1 IP (FPGA to ASIC)

Location
Southampton, England, United Kingdom
Zimmermann Company is seeking a Senior Verification Engineer to own UVM-based verification across complex communications IP, taking it from specification through to sign-off. You will work with architects, RTL designers and systems engineers to develop verification plans and build SystemVerilog/UVM environments. … will create coverage models, debug issues across RTL and verification environments, and contribute from early spec through final sign-off as the project scales for #J-18808-Ljbffr ...