Senior Verification Engineer
- Hiring Organisation
- Intellectual Capital Resources
- Location
- Edinburgh, Midlothian, United Kingdom
- Salary
- £ 60 K
functional and code coverage analysis SystemVerilog – SVA (SystemVerilog Assertions) Testbench design with verification frameworks like UVM/OVM, e, VMM Debugging skills – RTL – Testbench, OOP – Gate level (including SDF) Scripting experience with Ruby, sh/csh, TCL, Make, Perl Power aware verification (using CPF/UPF) This position is based ...