5 of 5 Permanent SystemVerilog Jobs in Newport

level and chip-level verification, including linting, synthesis, timing closure, CDC, RDC, and coverage analysis. Profile Essential Skills Degree in Computer Science, Engineering, or related field. Strong experience with SystemVerilog or VHDL . Competence in scripting (Python, Tcl). Knowledge of digital design flows. Desirable Experience Processor design and application-specific blocks. High-speed serial interfaces & complex third-party IP More ❯

and with top-tier industry partners. Key Responsibilities: Define digital architectures for AI accelerators, data paths, control logic, and SoC subsystems. Develop high-quality, synthesizable RTL in Verilog/SystemVerilog with performance, power, and area optimization in mind. Collaborate cross-functionally with verification, physical design, and packaging teams to ensure seamless integration. Leverage Cadence digital tools for synthesis, STA, and More ❯

architecture teams to ensure verification quality Qualifications Bachelor’s or Master’s in Electrical Engineering (or related field) Strong experience in ASIC verification and digital hardware design Skilled in SystemVerilog/UVM testbench development Knowledge of low-power verification techniques Familiarity with C for testbench development is a plus Experience in WiFi/wireless SoC development is desirable Excellent communication More ❯

Bachelor’s or Master’s degree in Electrical/Computer Engineering or related discipline. Proven track record in ASIC verification , ideally with experience in complex SoC designs. Proficiency in SystemVerilog and UVM methodology . WiFi or wireless SoC experience is highly desirable. Strong leadership skills with the ability to mentor and influence. Excellent communication and collaboration skills. What you’ll More ❯

growth reflects both long-term investment in R&D and a strategic shift in architecture, making it an exciting time to join. Principal Verification Engineer Responsibilities: Develop and maintain SystemVerilog UVM testbenches for complex IPs. Lead the creation of new UVM verification components and contribute to testbench architecture Debug test failures and define functional coverage models to ensure sign-off … verification strategy during design and concept phases. Improve verification efficiency and ensure compliance with functional safety and quality standards. Requirements: Minimum 5 years of IP-level verification experience using SystemVerilog UVM. Strong understanding of UVM methodology, SVAs, and verification metrics. Ability to interpret complex design specifications and create robust verification environments. Proficiency in industry-standard EDA tools and scripting languages. More ❯