2 of 2 Permanent UVM Jobs in the North of England

experienced verification engineer to join its Systems Media IP team in Manchester. You will own and drive verification for a DPU subsystem, architect reusable UVM environments and contribute to verification strategy across multiple units and teams. The role focuses on planning, integration, and sign-off with emphasis on regression efficiency ...

through sign-off. Contribute to the overall DPU verification architecture, planning, integration strategy and quality criteria. Architect reusable, scalable and high-performance SystemVerilog/UVM environments and verification IP. Define verification plans, coverage models, sign-off criteria and measurable quality goals for the owned verification scope. Identify technical and schedule … that the DPU integrates successfully into complete systems. Required Skills and Experience: Strong knowledge of, and extensive hands-on coding experience with, SystemVerilog and UVM, including the architecture, implementation and review of complex verification environments. Hands-on verification experience in standard on-chip bus protocols such as AMBA ...