FPGA Engineer
- Location
- Oxford, England, United Kingdom
such as pseudocode/Python/C++/MATLAB, into highly pipelined, resource-efficient FPGA RTL. RTL design from scratch: Design and implement custom digital logic using VHDL where off-the-shelf vendor IPs are insufficient, bottlenecked, or introduce latency. High-speed I/O integration: architect data acquisition … utilisation across multiple clock domains. Requirements Degree in Electrical Engineering, Computer Engineering, or a related field. 5+ years of hands-on experience in FPGA digital design, including designing and debugging resource-intensive high-speed digital systems. Expertise in HDL: Strong proficiency in HDL coding, and a proven track ...