Sr. Silicon Design Verification Engineer
- Location
- Penicuik, Scotland, United Kingdom
industry-standard simulation tools. Experience with Verilog, SystemVerilog, C, and C++. Experience developing UVM-based verification frameworks, reusable components, and verification methodologies. Experience with Python, Perl, Shell, Makefiles, or similar scripting languages. Familiarity with data analytics, workflow automation, and AI-enabled engineering practices. Experience applying AI/ML-assisted tools … verification, debug, coverage closure, or engineering productivity workflows. Experience using Python-based frameworks and AI-assisted development tools to improve engineering efficiency. Good understanding of SystemC and TLM; related experience is a plus. Exposure to networking, packet processing, Ethernet, SmartNIC, or networking processor architectures is highly desirable. Exposure to leadership ...