5 of 5 Permanent SystemVerilog Jobs in Reading

verification plans and develop automated test benches Create, document, and verify behavioral models of analog and analog-mixed-signal blocks (e.g., VerilogA/AMS, SystemVerilog-RNM, Wreal) to ensure they are optimized and up-to-date Design and verify Analog/RF blocks and sub-blocks (e.g., Transmitter ...

Mixed-Signal Verification, with demonstrated success delivering complex mixed-signal ICs right-first-time Experience in modelling analog subsystems using VerilogA/AMS/SystemVerilog Scripting experience with Python, sh/csh, TCL, Make A great team spirit, and excellent communication skills in English On offer is a competitive basic ...

improved. What They’re Looking For Experience managing or leading digital verification engineers Strong background in the verification of complex ICs Strong SystemVerilog and UVM experience, with knowledge of assertions and coverage-driven verification Experience developing verification strategies and using metrics such as code and functional coverage Ability to support ...

Location: Bristol, United KingdomThales is a global technology leader with more than 83,000 employees on five continents. With over 7,500 people in the UK, operating across defence, space, aerospace, and digital security, we ...

ASIC/SoC verification lifecycle, with real ownership of the verification of complex digital subsystems and mixed-signal ICs. Your work will include: Developing SystemVerilog/UVM verification environments Verification planning and test development Constrained-random and coverage-driven verification SVA/assertions Functional and code coverage RTL and testbench … senior levels What they're looking for You'll ideally have a background in ASIC, SoC or Digital IC Verification, with strong experience in: SystemVerilog | UVM | SVA | Constrained Random Verification | Functional Coverage | RTL Debug Experience with mixed-signal verification, formal verification, UPF/low-power verification, gate-level simulation ...