1 to 25 of 29 Permanent Verilog Jobs in Scotland

of working across the full life cycle Familiarity with latest FPGA device families and verification methodologies Proven expertise of developing FPGA using VHDL or Verilog Experienced with Mentor Graphics FPGA development tools including HDL Designer, ModelSim/Questa and Precision Familiar with Xilinx/Intel (Altera)/Microsemi (Actel) design More ❯

Experience using FPGA technologies from either Xilinx, Intel (Altera) or Microsemi (Actel) and their tools. Experience in verification techniques using either VHDL or System Verilog/UVM. Experience in specifying timing and area constraints for efficient FPGA place and route. Ability to analyse system level requirements and derive detailed firmware More ❯

development lifecycle to deliver customer requirements by: Developing high-level firmware requirements using DOORS Defining low level requirements and detailed designs Writing VHDL and Verilog HDL code using Sigasi Studio Simulating HDL designs at unit, integration and system level using Mentor Graphics QuestaSIM Undertaking synthesis, place and route and static More ❯

deliver customer requirements by: Developing high-level firmware requirements using DOORS Creating architectural designs Defining low level requirements and detailed designs Writing VHDL and Verilog HDL code using Sigasi Studio Simulating HDL designs at unit, integration and system level using Mentor Graphics QuestaSIM Undertaking synthesis, place and route and static More ❯

and dynamic team in our Design Centre in Edinburgh, Scotland. JOB RESPONSIBILITIES: Concept definition of digital architecture & blocks Specification writing RTL design & verification ((System)Verilog/VHDL) Close working with analog IC designers and sub-contractors Experience with design synthesis, timing closure & STA is desirable Support DfT strategy & implementation Debug More ❯

and dynamic team in our Design Centre in Edinburgh, Scotland. JOB RESPONSIBILITIES: Concept definition of digital architecture & blocks Specification writing RTL design & verification ((System)Verilog/VHDL) Close working with analog IC designers and sub-contractors Experience with design synthesis, timing closure & STA is desirable Support DfT strategy & implementation Debug More ❯

and dynamic team in our Design Centre in Edinburgh, Scotland. JOB RESPONSIBILITIES: Concept definition of digital architecture & blocks Specification writing RTL design & verification ((System)Verilog/VHDL) Close working with analog IC designers and sub-contractors Experience with design synthesis, timing closure & STA is desirable Support DfT strategy & implementation Debug More ❯

and dynamic team in our Design Centre in Edinburgh, Scotland. JOB RESPONSIBILITIES: Concept definition of digital architecture & blocks Specification writing RTL design & verification ((System)Verilog/VHDL) Close working with analog IC designers and sub-contractors Experience with design synthesis, timing closure & STA is desirable Support DfT strategy & implementation Debug More ❯

and dynamic team in our Design Centre in Edinburgh, Scotland. JOB RESPONSIBILITIES: Concept definition of digital architecture & blocks Specification writing RTL design & verification ((System)Verilog/VHDL) Close working with analog IC designers and sub-contractors Experience with design synthesis, timing closure & STA is desirable Support DfT strategy & implementation Debug More ❯

experience in: Strong low level embedded C programming skills. A solid grasp of C++. Experience in testing and integrating software with firmware (VHDL/Verilog) and hardware. Excellent debugging skills and application of various strategies. Use of RTOSs such as VxWorks or embedded Linux. Deployment of software to distributed hardware More ❯

have a real impact on designing some of the most exciting imaging systems being developed. You’ll need: Experience with RTL Design using VHDL, Verilog or Systemverilog Scripting knowledge with either Python, Perl or Tcl RTL verification experience is desirable Experience with FPGA prototyping would be valuable In return you More ❯

all levels welcome Proven experience verifying large System on Chip (SoC) designs. Expertise in DSP, Wireless Communication, and networking standards. Hands-on experience with Verilog, SystemVerilog, UVM, and/or VHDL. Strong verification mindset with in-depth knowledge of verification goals, practices, and methodologies. Practical experience with scripting languages such More ❯

all levels welcome Proven experience verifying large System on Chip (SoC) designs. Expertise in DSP, Wireless Communication, and networking standards. Hands-on experience with Verilog, SystemVerilog, UVM, and/or VHDL. Strong verification mindset with in-depth knowledge of verification goals, practices, and methodologies. Practical experience with scripting languages such More ❯

all levels welcome Proven experience verifying large System on Chip (SoC) designs. Expertise in DSP, Wireless Communication, and networking standards. Hands-on experience with Verilog, SystemVerilog, UVM, and/or VHDL. Strong verification mindset with in-depth knowledge of verification goals, practices, and methodologies. Practical experience with scripting languages such More ❯

all levels welcome Proven experience verifying large System on Chip (SoC) designs. Expertise in DSP, Wireless Communication, and networking standards. Hands-on experience with Verilog, SystemVerilog, UVM, and/or VHDL. Strong verification mindset with in-depth knowledge of verification goals, practices, and methodologies. Practical experience with scripting languages such More ❯

all levels welcome Proven experience verifying large System on Chip (SoC) designs. Expertise in DSP, Wireless Communication, and networking standards. Hands-on experience with Verilog, SystemVerilog, UVM, and/or VHDL. Strong verification mindset with in-depth knowledge of verification goals, practices, and methodologies. Practical experience with scripting languages such More ❯

at Leonardo: Strong low level embedded C programming skills. A solid grasp of C++. Experience in testing and integrating software with firmware (VHDL/Verilog) and hardware. Excellent debugging skills and application of various strategies. Use of RTOS's such as VxWorks or embedded Linux. Deployment of software to distributed More ❯

in development today. Key Responsibilities Define digital architecture and block-level concepts Develop detailed specifications for digital functions RTL design and verification using SystemVerilog, Verilog, or VHDL Collaborate closely with analog IC designers and subcontractors Debug RTL and gate-level simulation failures Write scripts in Python, Perl, or similar for More ❯

in development today. Key Responsibilities Define digital architecture and block-level concepts Develop detailed specifications for digital functions RTL design and verification using SystemVerilog, Verilog, or VHDL Collaborate closely with analog IC designers and subcontractors Debug RTL and gate-level simulation failures Write scripts in Python, Perl, or similar for More ❯

in development today. Key Responsibilities Define digital architecture and block-level concepts Develop detailed specifications for digital functions RTL design and verification using SystemVerilog, Verilog, or VHDL Collaborate closely with analog IC designers and subcontractors Debug RTL and gate-level simulation failures Write scripts in Python, Perl, or similar for More ❯

in development today. Key Responsibilities Define digital architecture and block-level concepts Develop detailed specifications for digital functions RTL design and verification using SystemVerilog, Verilog, or VHDL Collaborate closely with analog IC designers and subcontractors Debug RTL and gate-level simulation failures Write scripts in Python, Perl, or similar for More ❯

in development today. Key Responsibilities Define digital architecture and block-level concepts Develop detailed specifications for digital functions RTL design and verification using SystemVerilog, Verilog, or VHDL Collaborate closely with analog IC designers and subcontractors Debug RTL and gate-level simulation failures Write scripts in Python, Perl, or similar for More ❯

logical equivalency checking (LEC) · Verification debug support · Lint checks – RTL, CDC, RDC, DFT, UPF Required Skills & Knowledge: · Micro-architecture design, RTL coding in System Verilog for either of below blocks: o Power management control o Subsystem/SOC reset control o Subsystem/SOC clock control o Subsystem/SOC More ❯

logical equivalency checking (LEC) · Verification debug support · Lint checks – RTL, CDC, RDC, DFT, UPF Required Skills & Knowledge: · Micro-architecture design, RTL coding in System Verilog for either of below blocks: o Power management control o Subsystem/SOC reset control o Subsystem/SOC clock control o Subsystem/SOC More ❯

logical equivalency checking (LEC) · Verification debug support · Lint checks – RTL, CDC, RDC, DFT, UPF Required Skills & Knowledge: · Micro-architecture design, RTL coding in System Verilog for either of below blocks: o Power management control o Subsystem/SOC reset control o Subsystem/SOC clock control o Subsystem/SOC More ❯