5 of 5 Permanent SystemVerilog Jobs in Stevenage

FPGA Engineer

Hiring Organisation
Intellectual Capital Resources
Location
Stevenage, Hertfordshire, United Kingdom
Salary
£ 70 K
initial concept through to deployment. They are looking for an FPGA Engineer with the following background: FPGA development experience using VHDL and/or SystemVerilog Experience with Xilinx, Intel, or Microchip FPGA devices Understanding of FPGA verification methodologies and simulation tools Experience with FPGA design toolchains and timing closure Embedded ...

Senior/Staff Digital ASIC Design Engineer

Hiring Organisation
Intellectual Capital Resources
Location
Stevenage, Hertfordshire, United Kingdom
Salary
£ 70 K
techniques, including clock gating, while producing robust RTL code. Candidate profile Degree in Electrical/Electronic Engineering (MEng preferred) or equivalent Strong experience in SystemVerilog RTL design and verification across the full design and synthesis flow. Familiarity with synchronous and asynchronous design, and low-power techniques. Proficiency with Cadence ...

FPGA Designer

Hiring Organisation
MBDA
Location
Stevenage, Hertfordshire, UK
Employment Type
Full-time
Are you an experienced FPGA Designer who enjoys contributing to the development of complex FPGA platforms? Look no further! Join our ambitious team at MBDA and be part of a company that is at the ...

FPGA Designer

Hiring Organisation
MBDA
Location
Stevenage, Hertfordshire, United Kingdom
Salary
£ 55 K
Are you an experienced FPGA Designer who enjoys contributing to the development of complex FPGA platforms? Look no further! Join our ambitious team at MBDA and be part of a company that is at the ...

GPU Verification Engineer

Hiring Organisation
Intellectual Capital Resources
Location
Stevenage, Hertfordshire, United Kingdom
Salary
£ 120 K
enjoys digging into complex hardware problems and working closely with architecture and design. The work involves: Leading verification of GPU components and subsystems Developing SystemVerilog/UVM testbenches Defining verification plans and coverage strategy Writing tests, sequences, assertions and functional coverage Debugging complex RTL issues with design engineers Contributing … methodology and mentoring others They’re hoping to find someone with: Strong experience verifying complex RTL/ASIC/SoC designs Deep SystemVerilog and UVM experience Background building constrained-random environments Solid debugging and root-cause skills Familiarity with ASIC verification flows and closure It’s a small, highly technical ...