3 of 3 Permanent FPGA Design Jobs in the Thames Valley

Senior FPGA Engineer

Hiring Organisation
Jobleads-UK
Location
Oxford, England, United Kingdom
Senior FPGA Engineer Department: Engineering Employment Type: Full Time Location: Oxford Description We are looking for a Senior FPGA Engineer to architect, design, implement, and verify FPGA RTL for our optical interconnect development. The work centres on high-speed digital logic, video processing and framing … devices. This is a focused, senior RTL role that runs from architecture and RTL design through simulation, verification, and timing closure to FPGA bring-up and characterisation on the bench. You will own the FPGA design end to end and set the RTL standard ...

FPGA Design Engineer

Hiring Organisation
Platform Recruitment
Location
OX1, Oxford, Oxfordshire, United Kingdom
Employment Type
Permanent
Salary
£50000 - £70000/annum
FPGA Engineer Hybrid | Engineering & Software Development | Full-time | Oxford Salary: Up to £70,000 We are seeking a talented FPGA Engineer to join a pioneering quantum technology company in Oxford. You’ll help bring cutting-edge atom-based quantum devices from the lab to real-world applications. What … Design, implement, and test FPGA systems and real-time DSP algorithms Develop high-speed interfaces to hardware peripherals (ADC, DAC, DDS, PLL). Debug complex embedded systems combining hardware, firmware, and software. Collaborate with multidisciplinary teams to deliver next-generation quantum technologies. What We’re Looking ...

Senior FPGA Engineer — RTL Design, Verification & Bring-up (Relocation/Visa)

Hiring Organisation
Jobleads-UK
Location
Oxford, England, United Kingdom
Plessey in Oxford is seeking a Senior FPGA Engineer to architect, design, implement and verify FPGA RTL for high-speed digital, video, and optical-interfacing systems. You will own the FPGA design end-to-end and define RTL standards for others to follow. … will collaborate with electronics, RF, and photonics teams to bring prototypes toward product. The role emphasizes architecture, RTL design, verification, and timing closure across multiple clock domains. #J-18808-Ljbffr ...