1 to 25 of 30 Permanent Synopsys Jobs in the UK

and other physical verification compliance. Collaborate with DFT engineers to integrate design-for-test (DFT) structures into the physical implementation. Develop flows in EDA tools such as Cadence Innovus, Synopsys ICC2, Mentor Graphics Calibre, and others. Interface with foundries and process engineers to ensure manufacturability and yield optimisation. Work closely with RTL and architecture teams to drive design feasibility, constraints More ❯

and other physical verification compliance. Collaborate with DFT engineers to integrate design-for-test (DFT) structures into the physical implementation. Develop flows in EDA tools such as Cadence Innovus, Synopsys ICC2, Mentor Graphics Calibre, and others. Interface with foundries and process engineers to ensure manufacturability and yield optimisation. Work closely with RTL and architecture teams to drive design feasibility, constraints More ❯

with RISC-V instruction set architecture (preferred) Understanding of graphics pipelines and/or neural network accelerators Awareness of physical design implications (DFT, timing, floorplanning) Proficiency with EDA tools (Synopsys, Cadence, Mentor, etc.) Strong scripting skills in Python, TCL, or similar BS/MS in Electrical Engineering, Computer Engineering, or related field Verification Requirements: 5+ years of experience in hardware More ❯

verification. Proficiency in RTL design techniques, including synthesis, timing closure, and verification. Experience in using UVM for functional verification of ASIC designs. Experience with EDA tools like Cadence and Synopsys for design simulation and verification. Extensive experience with FPGA emulation, design tools, and verification. Contact: For further information please contact Mícheál at Software Placements on 00353 1 or email More ❯

SoCs. Partner with cross-functional teams to enable system bring-up, debug, and feature validation on emulation platforms. Support compilation, deployment, and debug flows for emulation systems such as Synopsys ZeBu, Cadence Palladium, and Siemens Strato. Solve simulation/emulation mismatches and system-level test failures. Work closely with EDA vendors to deploy new capabilities, resolve tool issues, and influence More ❯

and advance PPA. Key Requirements: 8+ years of experience within Physical Design, ideally with exposure to low-power design techniques. Experience with Cadence (Genus, Innovus, Tempus, QRC, Conformal) and Synopsys (Fusion Compiler, Formality) tools. Understanding in building flows and methodology using scripting languages such as TCL, Python, Perl to support project development. More ❯

and methodologies to improve GPU power, performance and area (PPA). Required Skills and Experience : Experience with hardware description languages (System Verilog preferable). Experience using EDA simulators (Siemens, Synopsys, Cadence) Strong problem solving and debugging skills, and ability to closely collaborate with other teams. Experience working with version control and code review systems such as Git and Gerrit Proficiency More ❯

are internationally renowned researchers from UCL and Oxford University who have pioneered the development of qubits and quantum computing architectures. Our chairman is the co-founder of Cadence and Synopsys, the two leading companies in the area of Electronic Design Automation. We're backed by a team of top-tier investors including Bosch Ventures, Porsche SE, Sony Innovation Fund, Oxford More ❯

environment. "Nice To Have" Skills and Experience : Experience with SoC-level build and integration flows, including flow optimization and maintenance. Solid understanding of industry-standard EDA tools such as Synopsys, Cadence, and Mentor. Exposure to design databases for storing, managing, and retrieving build logs and verification results. Familiarity with data representation formats such as YAML and JSON, and markup languages More ❯

ability to closely collaborate with hardware and software teams. Good written and verbal communication skills. Experience with hardware description languages (System Verilog preferable). Experience using EDA simulators (Siemens, Synopsys, Cadence) Experience working with version control and code review systems such as Git and Gerrit Experience with scripting languages such as Python, Perl, JSON, Tcl, Make etc. Motivated, dedicated and More ❯

Advantageous Qualifications Deep understanding of all aspects of Physical construction and Integration. Knowledge in Physical Design Verification methodology LVS/DRC. Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.). Great teammate, self-learning skills, and ability to work autonomously. , where each person is unique, but together we bring our talents to work as a team and More ❯

are internationally renowned researchers from UCL and Oxford University who have pioneered the development of qubits and quantum computing architectures. Our chairman is the co-founder of Cadence and Synopsys, the two leading companies in the area of Electronic Design Automation. We're backed by a team of top-tier investors including Bosch Ventures, Porsche SE, Sony Innovation Fund, Oxford More ❯

are internationally renowned researchers from UCL and Oxford University who have pioneered the development of qubits and quantum computing architectures. Our chairman is the co-founder of Cadence and Synopsys, the two leading companies in the area of Electronic Design Automation. Were backed by a team of top-tier investors including Bosch Ventures, Porsche SE, Sony Innovation Fund, Oxford Sciences More ❯

environment. "Nice To Have" Skills and Experience : Experience with SoC-level build and integration flows, including flow optimization and maintenance. Solid understanding of industry-standard EDA tools such as Synopsys, Cadence, and Mentor. Exposure to design databases for storing, managing, and retrieving build logs and verification results. Familiarity with data representation formats such as YAML and JSON, and markup languages More ❯

are internationally renowned researchers from UCL and Oxford University who have pioneered the development of qubits and quantum computing architectures. Our chairman is the co-founder of Cadence and Synopsys, the two leading companies in the area of Electronic Design Automation. We're backed by a team of top-tier investors including Bosch Ventures, Porsche SE, Sony Innovation Fund, Oxford More ❯

UK or abroad for technical reviews. What we need from you You should have experience in most of the below Design techniques using one or more of VPI, Ansys, Synopsys or similar simulation tool. Physical realisation of Photonics circuits or spread benches Derivation of and reporting against design requirements A structured approach to design Photonic test methods and equipment. Including More ❯

occasionally Go) to expose DevSecOps capabilities. Package and deploy services to OpenShift/Kubernetes clusters, ensuring scalability and high availability. DevSecOps Toolchain Integration Integrate with and extend APIs for Synopsys BlackDuck, Snyk, OWASP Dependency-Track, JFrog Artifactory, HashiCorp Vault/CyberArk, and more. Drive continuous improvement of our CI pipelines (Jenkins, TeamCity, Tekton), embedding security "shift-left" practices. Developer Enablement More ❯

Manager for this position, who is the SVP Sales, also has a preference for people from larger software companies. Target companies include the likes of: Sonatype, Checkmarx, GitLab, GitHub, Synopsys, Blackduck Software, QAsymphony, Parasoft, Dell Boomi, API Fortress, SmartBear Software, Datadog etc. Job Summary: The company provides DevOps solutions to thousands of customers, including the majority of the Fortune 100s. More ❯

as Genus, Innovus, Tempus, QRC, and Conformal. Proficient in physical design flows including synthesis, logical equivalence checking (LEC), floorplanning, placement, clock tree synthesis (CTS), routing, and STA. Familiarity with Synopsys Fusion Compiler and Formality tools. Knowledge of low power design methodologies including power gating and dynamic voltage and frequency scaling (DVFS). Ability to develop and maintain automation scripts using … Physical Design, RTL, Place and Route (PnR), Static Timing Analysis (STA), Logical Equivalence Checking (LEC), Low Power Design, Power Gating, DVFS, Cadence Genus, Cadence Innovus, Cadence Tempus, QRC, Conformal, Synopsys Fusion Compiler, Formality, Synthesis, Floorplanning, Placement, Clock Tree Synthesis (CTS), Routing, UPF, Constraint Development, EDA Tools, Automation Scripting, TCL, Python, Perl, Semiconductor, GPU Design If you are interested in this More ❯

how often (in days) to receive an alert: Date: Jul 7, 2025 Location: Cambridge, GB, CB1 7EG Company: Ansys Requisition #: 16326 Ansys is now a part of Synopsys. Synopsys, Inc. (Nasdaq: SNPS) accelerates technology innovation from silicon to systems. Catalyzing the era of pervasive intelligence, we deliver design solutions, from electronic design automation to silicon IP, to system design … total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Ansys, part of Synopsys, we want talented people of every background to feel valued and supported to do their best work. We consider all applicants for employment without regard to race, color, religion, national … origin, gender, sexual orientation, age, military veteran status, or disability. Stay safe from recruitment fraud! We are aware of scams targeting Ansys, part of Synopsys and other companies that involve individuals posing as employees to illegitimately conduct interviews and extend false employment offers and payments to gain access to candidates' sensitive personal and financial information. All Ansys job applicants are More ❯

precision bias circuits and fractional-N PLLs to support system-level integration. Work with SiGe and CMOS process technologies to achieve optimal analogue performance. Use industry-standard tools (Cadence, Synopsys) for schematic entry, layout supervision, and verification. Collaborate with layout engineers, validation teams, and system architects to ensure successful silicon implementation and debug. Qualifications and Skills required for this Senior … Design, or a related field, with extensive experience in IC design. Strong background in analogue circuit design including references, PLLs, and passive/active filters. Experience with Cadence or Synopsys tool suites for design and verification. Familiarity with SiGe and CMOS technology platforms. Good understanding of analogue performance metrics such as linearity, PSRR, and noise. Effective communicator and team player More ❯

precision bias circuits and fractional-N PLLs to support system-level integration. Work with SiGe and CMOS process technologies to achieve optimal analogue performance. Use industry-standard tools (Cadence, Synopsys) for schematic entry, layout supervision, and verification. Collaborate with layout engineers, validation teams, and system architects to ensure successful silicon implementation and debug. Qualifications and Skills required for this Senior … Design, or a related field, with extensive experience in IC design. Strong background in analogue circuit design including references, PLLs, and passive/active filters. Experience with Cadence or Synopsys tool suites for design and verification. Familiarity with SiGe and CMOS technology platforms. Good understanding of analogue performance metrics such as linearity, PSRR, and noise. Effective communicator and team player More ❯

precision bias circuits and fractional-N PLLs to support system-level integration. Work with SiGe and CMOS process technologies to achieve optimal analogue performance. Use industry-standard tools (Cadence, Synopsys) for schematic entry, layout supervision, and verification. Collaborate with layout engineers, validation teams, and system architects to ensure successful silicon implementation and debug. Qualifications and Skills required for this Senior … Design, or a related field, with extensive experience in IC design. Strong background in analogue circuit design including references, PLLs, and passive/active filters. Experience with Cadence or Synopsys tool suites for design and verification. Familiarity with SiGe and CMOS technology platforms. Good understanding of analogue performance metrics such as linearity, PSRR, and noise. Effective communicator and team player More ❯

precision bias circuits and fractional-N PLLs to support system-level integration. Work with SiGe and CMOS process technologies to achieve optimal analogue performance. Use industry-standard tools (Cadence, Synopsys) for schematic entry, layout supervision, and verification. Collaborate with layout engineers, validation teams, and system architects to ensure successful silicon implementation and debug. Qualifications and Skills required for this Senior … Design, or a related field, with extensive experience in IC design. Strong background in analogue circuit design including references, PLLs, and passive/active filters. Experience with Cadence or Synopsys tool suites for design and verification. Familiarity with SiGe and CMOS technology platforms. Good understanding of analogue performance metrics such as linearity, PSRR, and noise. Effective communicator and team player More ❯

precision bias circuits and fractional-N PLLs to support system-level integration. Work with SiGe and CMOS process technologies to achieve optimal analogue performance. Use industry-standard tools (Cadence, Synopsys) for schematic entry, layout supervision, and verification. Collaborate with layout engineers, validation teams, and system architects to ensure successful silicon implementation and debug. Qualifications and Skills required for this Senior … Design, or a related field, with extensive experience in IC design. Strong background in analogue circuit design including references, PLLs, and passive/active filters. Experience with Cadence or Synopsys tool suites for design and verification. Familiarity with SiGe and CMOS technology platforms. Good understanding of analogue performance metrics such as linearity, PSRR, and noise. Effective communicator and team player More ❯