1 to 25 of 89 Permanent SystemVerilog Jobs in the UK excluding London

verification efficiency and coverage. Required Skills and Experience: Solid understanding of SoC verification using C test cases, hardware description, and verification languages such as SystemVerilog, Verilog, or VHDL. Knowledge of computer architecture, bus protocols (e.g., AXI, AHB), and peripherals. Experience with Tcl, Python, or other scripting languages. Nice-to-Have More ❯

Job Overview: We are looking for an FPGA/Embedded-Systems Engineer to join Arm's Solution Engineering FPGA Design team on a permanent basis. The team is based in Cambridge UK, working at the forefront of Arm based embedded More ❯

DSP, or FPU architectures and debugging/testing strategies. Hands-on experience with ASIC, FPGA, and physical design tools (P&R). Proficiency in SystemVerilog, C, SystemC, C++, Python, Perl, or TCL. Knowledge of place and route methodologies. Strong communication skills, both written and spoken, in English. Who we are More ❯

subject FPGA or ASIC architecture, design and verification, including: System engineering and partition IP Design, Packaging and Integration Xilinx Vivado or Altera Quartus Verilog, SystemVerilog Timing Closure Self-checking/Automated Testbenches integrated into CI Electronic design experience including high-speed design and high-level layout Technical leadership experience Knowledge More ❯

speed I/O like GTM and F-Tile transceivers Expertise in FPGA tool flows: synthesis, partitioning, place & route, timing analysis Strong skills in SystemVerilog, Verilog, VHDL, and scripting (tcl and Python) Experience with high-performance FPGA devices such as Xilinx Versal Premium or Intel Agilex 7 If you're More ❯

speed I/O like GTM and F-Tile transceivers Expertise in FPGA tool flows: synthesis, partitioning, place & route, timing analysis Strong skills in SystemVerilog, Verilog, VHDL, and scripting (tcl and Python) Experience with high-performance FPGA devices such as Xilinx Versal Premium or Intel Agilex 7 If you're More ❯

embedded C/C++ based SoC verification environments. Knowledge of assembly language (preferably ARM), C/C++ and/or hardware verification languages e.g. (SystemVerilog), shell programming/scripting (e.g. Tcl, Perl, Python etc.). Experienced in one or more of various verification methodologies - UVM/OVM, formal, low power More ❯

Science (CS), or a related technical field. Prior experience in designing, coding, testing, and verifying FPGAs and/or ASICs. Proficiency in VHDL, Verilog, SystemVerilog, as well as C or C++ programming languages. Familiarity with RTL synthesis and the ability to write timing, area, and other pertinent constraints. Experience working More ❯

Experience Defence domain experience or relevant experience in the Aerospace industry Development and certification of airborne equipment New Product Introduction experience Independent verification using SystemVerilog/UVM Experience of embedded processor cores (e.g. ARM) in FPGA designs Qualifications Honours degree or equivalent in Electronics Engineering or another STEM-based subject More ❯

Experience Defence domain experience or relevant experience in the Aerospace industry Development and certification of airborne equipment New Product Introduction experience Independent verification using SystemVerilog/UVM Experience of embedded processor cores (e.g. ARM) in FPGA designs Qualifications Honours degree or equivalent in Electronics Engineering or another STEM-based subject More ❯

/documentation Desirable Development of real-time, embedded, safety-critical firmware, preferably in accordance with RTCA/DO-254 DAL D Independent verification using SystemVerilog/UVM Relevant experience in the Aerospace or Defence industry Experience of embedded processor cores (e.g. ARM) in FPGA designs Familiarity with latest FPGA device More ❯

might also have experience of one or more of the following: Build systems (e.g. Bazel, Nextflow, FuseSoC) Hardware EDA tools (eg. simulation, linting, synthesis) Systemverilog, C/C++, Simulator DPI/VPI Containerization (eg. Docker) Distributed Compute, Orchestration Jenkins Automation Software templating, rendering Data Engineering/Data Science/Machine More ❯

real impact on designing some of the most exciting imaging systems being developed. You’ll need: Experience with RTL Design using VHDL, Verilog or Systemverilog Scripting knowledge with either Python, Perl or Tcl RTL verification experience is desirable Experience with FPGA prototyping would be valuable In return you’ll get More ❯

language. Understanding of computer architecture fundamentals, such as pipelining, exception handling, memory systems. Perhaps some practical experience of working on microprocessor designs. Familiarity with SystemVerilog, maybe using a methodology such as UVM. Python programming experience, for example to automate verification flows. C++ programming experience, maybe in the context of a More ❯

language. Understanding of computer architecture fundamentals, such as pipelining, exception handling, memory systems. Perhaps some practical experience of working on microprocessor designs. Familiarity with SystemVerilog, maybe using a methodology such as UVM. Python programming experience, for example to automate verification flows. C++ programming experience, maybe in the context of a More ❯

Instruments LabVIEW-based equipment. Performing hands-on testing of devices using National Instruments LabVIEW-based equipment in the Plymouth lab facility. Designing and verifying SystemVerilog RTL targeting FPGA implementations. Creating schematics for test boards and fixtures. Recording and analyzing product test results and equipment logs. The Impact You Will Have More ❯

Instruments LabVIEW-based equipment. Performing hands-on testing of devices using National Instruments LabVIEW-based equipment in the Plymouth lab facility. Designing and verifying SystemVerilog RTL targeting FPGA implementations. Creating schematics for test boards and fixtures. Recording and analyzing product test results and equipment logs. The Impact You Will Have More ❯

Knowledge and experience of safety standards such as IEC 61513, IEC 62566, IEC 26262, DO-254 UVM Constrained Random Testing Formal Verification Languages: VHDL, SystemVerilog, TCL, Python We're an equal opportunities employer. We're committed to developing a diverse workforce and an inclusive working environment. We believe that people More ❯

levels welcome Proven experience verifying large System on Chip (SoC) designs. Expertise in DSP, Wireless Communication, and networking standards. Hands-on experience with Verilog, SystemVerilog, UVM, and/or VHDL. Strong verification mindset with in-depth knowledge of verification goals, practices, and methodologies. Practical experience with scripting languages such as More ❯

levels welcome Proven experience verifying large System on Chip (SoC) designs. Expertise in DSP, Wireless Communication, and networking standards. Hands-on experience with Verilog, SystemVerilog, UVM, and/or VHDL. Strong verification mindset with in-depth knowledge of verification goals, practices, and methodologies. Practical experience with scripting languages such as More ❯

Knowledge and experience of safety standards such as IEC 61513, IEC 62566, IEC 26262, DO-254 UVM Constrained Random Testing Formal Verification Languages: VHDL, SystemVerilog, TCL, Python The package: You'll receive a very competitive salary (£££ offered depends on level of experience) and other benefits including pension, life assurance and More ❯

determine verification requirements from the analysis of specifications Experience of debug and testing methodologies Experience with industry-standard verification methodologies and tools (UVM/SystemVerilog, Tools like VCS/Cadence/Questa) Experience in version control systems (e.g., Git/Mercurial/Perforce/Subversion) You might also have: A More ❯

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field Solid understanding and hands-on experience with UVM and SystemVerilog Proficiency in scripting languages such as Perl, Python, or TCL Mid-Senior level As a Design Verification Engineer, the individual will spend their days collaborating More ❯

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field Solid understanding and hands-on experience with UVM and SystemVerilog Proficiency in scripting languages such as Perl, Python, or TCL Mid-Senior level As a Design Verification Engineer, the individual will spend their days collaborating More ❯

of verifying CPU architectures or other complex IP (e.g. GPUs, NNAs) Fluency and the ability to write clear and concise code in languages like SystemVerilog, Python, C++, Rust, or Go Past verification ownership of a design block Analytical thinking, self-sufficiency and team collaboration skills Ability to work effectively across More ❯