101 to 125 of 481 Permanent C Jobs

Experience in Verilog/SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would ...

Experience in Verilog/SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would ...

Experience in Verilog/SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would ...

Experience in Verilog/SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would ...

Experience in Verilog/SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would ...

Experience in Verilog/SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would ...

Experience in Verilog/SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would ...

Experience in Verilog/SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would ...

engineer or electronics engineer with transferable talent into software development for test solutions: Strong ability to write software in one of the following languages; C, C++ or ADA and motivated to develop reliable, high performance, standardised and documented software Excellent analytical and design ability, including review and critical analysis ...

Experience in Verilog/SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would ...

Experience in Verilog/SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would ...

Experience in Verilog/SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would ...

Experience in Verilog/SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would ...

Experience in Verilog/SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would ...

Experience in Verilog/SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would ...

Experience in Verilog/SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would ...

Experience in Verilog/SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would ...

Experience in Verilog/SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would ...

Experience in Verilog/SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would ...

Experience in Verilog/SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would ...

field with 8+ years of relevant experience OR Master's degree with 6+ years of relevant experience Strong object-oriented programming experience Proficiency in C, C++, and/or Ada (Ada preferred but not required) Experience developing real-time, multi-threaded systems Familiarity with Linux (Red Hat), virtual machines ...

will bring experience across areas such as: Threat intelligence models (Pyramid of Pain, IPCE, TI lifecycle) Detection engineering & alert development Scripting skills (Python, Bash, C/C++, Java) Core cybersecurity fundamentals: network, cloud, cryptography, forensics Understanding of attacker techniques, APT behaviours and network protocol abuse Familiarity with Windows/Linux ...

seeking a Quantum Software Engineer (m/f/d) to join an interdisciplinary team of HPC experts in the working group "Computing" (AG C) with a regular working week of 39 hours (100%). Remuneration is in accordance with the collective agreement for the German public service (federal government ...

planning and operational management Support business development efforts, including proposal writing and technical briefings Essential Skills and Experience Proficiency in programming languages such as C, C++, or Python Strong working knowledge of Linux-based systems, including command-line tools and system configuration Excellent communication skills, both written and verbal Solid ...

Configuration Control using GIT or similar tool Educated to Degree/HND level in an appropriate subject. Desirable Criteria: Proficiency in the following languages: C, C++, Python, Java Script, MISRA C. Experience of developing for following OS’s: Linux, VxWorks Experience of Bare Metal SW development Experience Model based development ...