76 to 100 of 481 Permanent C Jobs

critical software. Background - Senior Staff Software Engineer Bachelor’s or master’s level education Significant experience in aerospace or safety-critical systems. Proficiency in C/C++ for embedded systems. Experience with writing software for flight control electronics. Expertise in deterministic, fault-tolerant systems. Understanding of DO-178C certification ...

deliver high-quality solutions Essential Requirements Experience with AWS development and deployment Experience working with AWS Lambda Strong programming experience with Python, Java, JavaScript, C or C++ Experience using appropriate software testing frameworks Experience with modern development tools including Git, GitLab, GitLab CI, and JIRA A strong interest in technology ...

secure coding practices, maintain high standards of software quality and work closely with operating systems at a low level. Key Requirements * Strong experience with C or C++ * Familiarity with Python * Comfortable working with Linux or Windows operating systems * Knowledge of version control tools and experience in agile delivery environments ...

deliver high-quality solutions Essential Requirements Experience with AWS development and deployment Experience working with AWS Lambda Strong programming experience with Python, Java, JavaScript, C or C++ Experience using appropriate software testing frameworks Experience with modern development tools including Git, GitLab, GitLab CI, and JIRA A strong interest in technology ...

good experience across a range of these areas: Degree in Electronics Engineering, Embedded Systems, Computer Engineering, Mechatronics, or equivalent experience Strong foundation in embedded C/C++, microcontroller programming, and real-time firmware concepts Hands-on experience with common microcontroller platforms (e.g., ARM Cortex-M, ESP32, AVR, SAMD) Understanding ...

diagnostic algorithms? Your background as a Software Engineer: Degree in Computer Science, Software Engineering, Electronic Engineering or similar (2.1 or above). Experience with C/C++, Python, MATLAB or similar Understanding of software development best practices (structured design, testing, version control) Exposure to algorithm development, data processing, or mathematical ...

Europe. This will include the following job title example and technology but not limited to: Electronic Engineers: Hardware/Software/Firmware. Embedded C, C++, C#, Embedded Linux, ARM , UNIX, RTOS, 3G, Application and Driver Development (inc Mobile), DSP, Algorithms, Audio, Video, Streaming, Symbian, ADA, STB, DVB, DTV, IPTV ...

systems, infrastructure, and scripting (Bash, Shell, Python) Strong understanding of containerisation and virtualisation Experience integrating software within large or distributed systems Working knowledge of C/C++ and Java (Python desirable) Understanding of software architectures and TCP/IP networking Experience with: Software integration and system-level testing Unit ...

Experience in Verilog/SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would ...

Experience in Verilog/SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would ...

Experience in Verilog/SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would ...

Experience in Verilog/SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would ...

Experience in Verilog/SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would ...

Experience in Verilog/SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would ...

Experience in Verilog/SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would ...

Experience in Verilog/SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would ...

Experience in Verilog/SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would ...

Experience in Verilog/SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would ...

Experience in Verilog/SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would ...

Experience in Verilog/SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would ...

Experience in Verilog/SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would ...

Experience in Verilog/SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would ...

Experience in Verilog/SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would ...

Experience in Verilog/SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would ...

Experience in Verilog/SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would ...