Principal Engineer, Design Verification
- Hiring Organisation
- Analog Devices
- Location
- Edinburgh, Midlothian, United Kingdom
- Salary
- £ 60 K
generating verification-plans and closure metrics.Debugging of Gate Level Simulation (GLS), waiving Timing Violations approved by designerContinuous interaction with analog co-sim and firmware team.Technically mentor and guide junior verification engineers on SoC Verification.Support post-silicon verification activities of the products working with design, product evaluation and applications engineering teamLead ...