1 to 25 of 28 Remote/Hybrid SystemVerilog Jobs in Cambridge

Linux and/or Windows development environments . Bonus Experience Xilinx SoC platforms (e.g. Zynq, Versal) Intel (Altera) FPGA architectures, including SoCs Verilog/SystemVerilog Cryptographic algorithms or secure hardware systems Product compliance, certification, or regulated environments Personal Attributes Demonstrates ownership and accountability for technical delivery. Applies a structured approach ...

your experience.Interested? You will naturally have a strong relevant CV with significant commercial-grade experience, demonstrating your skills with Vivado/Quartus and SystemVerilog, Verilog or VHDL. Send it to ECM where it will receive close confidential review. We do read every CV, and try to respond to everyone.Please note ...

protocols.Provide technical mentorship and support to less experienced engineers.Required Skills and Experience5+ years of experience in IP, subsystem, or SoC verification.Strong proficiency in SystemVerilog and Verilog.Experience with UVM or other industry-standard verification methodologies.Experience developing constrained-random verification environments and reusable verification components.Experience developing verification strategies and test protocols.Understanding ...

like side‐channel or fault attacks. Excellent collaboration, communication, and documentation skills. Nice To Have: Familiarity with hardware design flows (e.g., RTL, UVM/SystemVerilog). Exposure to TPMs, Secure Elements, or hardware‐backed crypto modules. Background in academic research or industry work in embedded security, firmware, or cryptographic implementation. ...

complex SoC developmentExperience in static design checks, including CDC, RDC, X-prop, Lint and UPF static checksExperience creating design specificationsExperience with Verilog/SystemVerilog and verification methodologiesStrong delivery record of sophisticated RTL subsystems in reasonable timescalesAbility to navigate and make high-level analysis driven PPA trade-offs along with driving ...

drive root-cause analysis of issues identified throughout the verification process.Required Skills and Experience :Experience building verification environments for sophisticated RTL designs.Strong proficiency in SystemVerilog and scripting languages such as Python, Perl, or Tcl.Proven grasp of the complete verification process, starting from test planning and continuing through to verification closure.Ability ...

surfaces like side-channel or fault attacks.Excellent collaboration, communication, and documentation skills.“Nice To Have” :Familiarity with hardware design flows (e.g., RTL, UVM/SystemVerilog).Exposure to TPMs, Secure Elements, or hardware-backed crypto modules.Background in academic research or industry work in embedded security, firmware, or cryptographic implementation.Discovering or analysing ...

cause analysis of issues identified throughout the verification process. Required Skills and Experience :Experience building verification environments for sophisticated RTL designs. Strong proficiency in SystemVerilog and scripting languages such as Python, Perl, or Tcl. Proven grasp of the complete verification process, starting from test planning and continuing through to verification ...

performance and reliability.Required Skills and Experience:8+ years of experience in RTL build, microarchitecture, subsystem integration, or related semiconductor roles.Deep hands-on expertise in SystemVerilog and the development of sophisticated, high-performance digital subsystems.Deep understanding of PCIe, CXL, and UALink, covering transaction flows, ordering, flow control, retries, error handling, host ...

reliability. Required Skills And Experience 8+ years of experience in RTL build, microarchitecture, subsystem integration, or related semiconductor roles. Deep hands-on expertise in SystemVerilog and the development of sophisticated, high-performance digital subsystems. Deep understanding of PCIe, CXL, and UALink, covering transaction flows, ordering, flow control, retries, error handling ...

will configure Deltaflow Hardware, ensuring low-latency, high-throughput connections essential for quantum experiments. The ideal candidate has experience with FPGA platforms, proficiency in SystemVerilog or VHDL, and strong communication skills. This role offers a hybrid working environment and opportunities for personal and professional growth. #J-18808-Ljbffr ...

/emulation mismatches and test failures. Hands-on experience with emulation platforms such as ZeBu, Palladium, or Strato. Familiarity with RTL languages such as SystemVerilog/Verilog Experience in collaboration with EDA vendors to introduce new capabilities, resolve tool issues, and contribute to future tool improvements. Skilled in planning system ...

troubleshooting simulation/emulation mismatches and test failures.Hands-on experience with emulation platforms such as ZeBu, Palladium, or Strato.Familiarity with RTL languages such as SystemVerilog/VerilogExperience in collaboration with EDA vendors to introduce new capabilities, resolve tool issues, and contribute to future tool improvements.Skilled in planning system test tasks ...

open-source silicon team. This permanent, hybrid role offers involvement in OpenTitan Root of Trust and Ibex CPU verification. You will develop and debug SystemVerilog/UVM testbenches, create verification plans, and collaborate with design engineers to deliver high-quality silicon, while contributing to open-source projects and robust verification ...

Join us at Entrust At Entrust, we’re shaping the future of identity centric security solutions. From our comprehensive portfolio of solutions to our flexible, global workplace, we empower careers, foster collaboration, and build solutions ...

Join us at Entrust At Entrust, we're shaping the future of identity centric security solutions. From our comprehensive portfolio of solutions to our flexible, global workplace, we empower careers, foster collaboration, and build solutions ...

Job Overview:Arms Solution Engineering division develops SoCs for various application segments, using the latest IP products from Arm and other vendors. We are looking for a creative and hard-working SoC Design Engineer to ...

discipline, you will have 10+ years of relevant industry experience and demonstrate: Extensive hands-on experience in digital RTL design and microarchitecture development using SystemVerilog and/or Verilog. A strong delivery record of sophisticated IP or RTL subsystem designs. Deep understanding of RTL design techniques and methodologies for complex … AMBA protocols. Experience with advanced low-power RTL design and power-aware verification, including power/clock gating, retention and DVFS. Proficiency with SystemVerilog Assertions (SVA) and formal verification techniques, and UVM Knowledge of Functional Safety methodologies and safety-related hardware design. Experience developing or improving RTL, IP and subsystem ...

Job Overview Arm Solution Engineering organization delivers complex solutions from systems specifications, through FE & validation, physical implementation and silicon. Join our dynamic Front End design team, a key part of Arm's SE SoC Engineering ...

About SiFive As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive ...

Job OverviewArm Solution Engineering organization delivers complex solutions from systems specifications, through FE & validation, physical implementation and silicon.Join our dynamic Front End design team, a key part of Arm's SE SoC Engineering!We are ...

member of the verification team, you will:Develop and own verification plans for IP blocks based on architecture and build specificationsBuild and implement SystemVerilog/UVM-based verification environments, including testbenches, stimulus, and checkersDefine functional and code coverage goals and drive coverage closureDebug RTL and verification issues, working closely with … ensure delivery of high-quality IPNecessary Skills and ExperienceYou will possess:Experience in RTL verification, including development of constrained-random environmentsStrong proficiency in SystemVerilog and familiarity with UVM or similar methodologiesExperience in writing test plans, developing testbenches, and driving coverage closureGood debugging and problem-solving skills in complex simulation environmentsUnderstanding ...

Job Overview: We are looking for a hard-working, creative and motivated engineer to join our GPU development team! We need someone who can work closely with the block design teams, crafting and implementing new ...

Job Overview:We are looking for a hard-working, creative and motivated engineer to join our GPU development team! We need someone who can work closely with the block design teams, crafting and implementing new ...

work alongside experienced engineers, helping to develop robust verification environments while gaining exposure to production silicon and advanced verification methodologies. Responsibilities Develop and debug SystemVerilog/UVM testbenches. Create and execute verification plans, tests, and coverage. Debug simulation failures and support regression testing. Contribute to verification infrastructure and automation. Collaborate … quality silicon. Participate in code reviews and contribute to open-source projects. Requirements 1–5 years' industry experience in Digital Design Verification. Experience with SystemVerilog and UVM. Understanding of verification methodologies and constrained-random verification. Experience writing testbenches and debugging RTL. Programming experience in Python and/or C. Familiarity ...