Design Verification Engineer
- Hiring Organisation
- IC Resources
- Location
- Cambridge, Cambridgeshire, UK
- Employment Type
- Full-time
level verification. Key Responsibilities Develop comprehensive core verification plans based on micro-architecture and design specifications. Architect and implement robust, reusable verification environments using SystemVerilog and UVM. Create and execute constrained-random and directed tests to achieve high levels of functional and code coverage. Analyse simulation results, debug complex failures … design teams to root-cause and resolve issues. Develop and maintain Python and Perl scripts to improve verification flows and regression management. Requirements Strong SystemVerilog/UVM expertise (essential). Solid understanding of digital logic design and verification methodologies. Experience verifying digital systems using standard IP components and interconnects. Project ...