10 of 10 Remote/Hybrid UVM Jobs in Cambridge

attack surfaces like side‐channel or fault attacks. Excellent collaboration, communication, and documentation skills. Nice To Have: Familiarity with hardware design flows (e.g., RTL, UVM/SystemVerilog). Exposure to TPMs, Secure Elements, or hardware‐backed crypto modules. Background in academic research or industry work in embedded security, firmware ...

System level team focused on PCIe and CXL verification and performance analysis. You will craft test plans, build SystemVerilog/Verilog/UVM testbenches, and debug complex test failures to ensure robust IO verification. You will collaborate with RTL architects, verification engineers and PMs across global sites to define verification ...

concepts clearly to a range of audiences."Nice To Have" Skills and Experience :Solid knowledge of Arm architecture. Experience with verification methodologies such as UVM or equivalent experience. Programming experience in C/C++ and Python. Practical experience verifying microprocessor or CPU designs. Understanding of constrained-random stimulus, functional coverage ...

less experienced engineers. Required Skills and Experience5+ years of experience in IP, subsystem, or SoC verification. Strong proficiency in SystemVerilog and Verilog. Experience with UVM or other industry-standard verification methodologies. Experience developing constrained-random verification environments and reusable verification components. Experience developing verification strategies and test protocols. Understanding ...

experienced engineers, helping to develop robust verification environments while gaining exposure to production silicon and advanced verification methodologies. Responsibilities Develop and debug SystemVerilog/UVM testbenches. Create and execute verification plans, tests, and coverage. Debug simulation failures and support regression testing. Contribute to verification infrastructure and automation. Collaborate closely with ...

functional environment."Nice To Have" Skills and Experience :Experience with GPU, CPU or other complex processor architectures. Familiarity with verification methodologies including System Verilog, UVM or formal verification. Experience with industry-standard EDA tools (e.g. Cadence or Synopsys).Knowledge of requirements management tools such as Jama, DRM or similar. Exposure ...

silicon team. This permanent, hybrid role offers involvement in OpenTitan Root of Trust and Ibex CPU verification. You will develop and debug SystemVerilog/UVM testbenches, create verification plans, and collaborate with design engineers to deliver high-quality silicon, while contributing to open-source projects and robust verification environments. #J ...

synthesis Desirable: Knowledge of communications signal processing algorithms (such as error correction, equalisation, channel estimation, beamforming) Familiarity with the AMBA bus protocols Understanding of UVM verification techniques or practical experience using UVM for IP verification Experience using C++/SystemC for design modelling and integration Experience with high speed interfaces ...

architecture and design specifications, and to build a functional verification strategy. Your key responsibilities will include crafting test plans, developing SystemVerilog/Verilog/UVM testbenches and tests, and debugging of test failures and issues. You will also be to developing and improving the verification methodologies used by the team. … Experience on working with PCIe & CXL IPs and Emulation friendly Transactors. Experience on simulation and emulation platforms. Good debugging experience using debuggers. Expertise in UVM based verification. Good knowledge of verification strategies like test plan creation, tasks tracking, coverage and verification sign-off. Knowledge on formal methodology. “Nice To Have ...

verification team, you will: Develop and own verification plans for IP blocks based on architecture and build specificationsBuild and implement SystemVerilog/UVM-based verification environments, including testbenches, stimulus, and checkersDefine functional and code coverage goals and drive coverage closureDebug RTL and verification issues, working closely with build and architecture … high-quality IPNecessary Skills and ExperienceYou will possess: Experience in RTL verification, including development of constrained-random environmentsStrong proficiency in SystemVerilog and familiarity with UVM or similar methodologiesExperience in writing test plans, developing testbenches, and driving coverage closureGood debugging and problem-solving skills in complex simulation environmentsUnderstanding of verification fundamentals ...