10 of 10 Remote UVM Jobs in Cambridge

Skills and Experience: Experience with ARM-based designs and/or ARM System Architectures. Familiarity with ARM debugger and trace features e.g ARM DS, DSTREAM. Experience with verification methodologies - UVM/OVM. Knowledge of PCIe and CXL will be a plus. Accommodations at Arm At Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation More ❯

work experience. OR PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience. Preferred Skills: • Simulation based verification using UVM/System Verilog What's on Offer Apart from working in an open, relaxed and collaborative space, you will enjoy: Salary, stock and performance related bonus Employee stock purchase scheme More ❯

interpret security tests. Experience with advanced attack vectors like side-channel and fault attacks. Strong collaboration, communication, and documentation skills. Nice To Have: Knowledge of hardware design flows (RTL, UVM/SystemVerilog). Experience with TPMs, Secure Elements, or cryptographic modules. Background in embedded security research or industry. Experience in vulnerability discovery and analysis, including CVEs. Familiarity with certification schemes More ❯

Engineering, or Computer Science. Solid understanding of emulation methodologies and flows. Experience with emulation platforms such as ZeBu, Palladium, or Strato. Familiarity with RTL languages (SystemVerilog/Verilog) and UVM-based verification environments. Hands-on experience in compiling and debugging large-scale designs on emulation platforms. Proficiency in scripting (Python, Perl, or similar) to automate workflows and diagnostics. Excellent problem More ❯

Engineering, or Computer Science. Solid understanding of emulation methodologies and flows. Experience with emulation platforms such as ZeBu, Palladium, or Strato. Familiarity with RTL languages (SystemVerilog/Verilog) and UVM-based verification environments. Hands-on experience in compiling and debugging large-scale designs on emulation platforms. Proficiency in scripting (Python, Perl, or similar) to automate workflows and diagnostics. Excellent problem More ❯

Debugging failures - interacting with design, verification and software driver teams Required Skills and Experience : Experience in hardware verification methodology and planning Programming skills including Hardware Description Languages (SystemVerilog/UVM) Proficiency in problem solving and debugging "Nice To Have" Skills and Experience : Experience with reusing and integrating external VIPs Experience in Python and Scala Willingness to travel to other Arm More ❯

design and verification flow. This includes: Working closely with the RTL design team to develop comprehensive verification strategies Creating and reviewing design verification documentation Designing and implementing SystemVerilog/UVM based verification IP and testbenches Improving existing testbenches to increase performance, quality and efficiency Testing and debugging Verilog RTL Defining and implementing functional coverage as well as enhancing the testbench … planned time Driving the execution to ensure the design work quality Required Skills and Experience Experience in RTL verification Proficiency in a hardware verification language, preferably System Verilog/UVM Experience of development of coverage-driven constrained random test environments Understanding of computer architecture fundamentals Strong interpersonal skills and ability to work well as part of a team "Nice To More ❯

Job Overview As part of Arm's continued growth, the CPU team are looking to hire dedicated engineers to join our Cambridge team. You will be working on next generation CPU products in close collaboration with the Cambridge team. We More ❯

packages and driving them to success. Required Skills and Experience: Meticulous attention to detail, ensuring high-quality verification that minimizes bug escapes. Shown experience in block-level verification using UVM or similar methodologies. Strong knowledge of coverage driven verification for complex designs. Proficient in specifying, creating, and debugging SystemVerilog/UVM constrained-random testbenches. Skilled in planning verification tasks and More ❯

all phases of the verification flow in order to ensure the high-quality and on time deliveries. Required Skills and Experience Strong hands-on experience in System Verilog and UVM methodology OR formal verification Exposure to all stages of unit verification: collection of requirements, defining test methodologies, writing test plans, developing testbenches and test cases, debugging complex designs and testbenches … coverage closure. Excellent communication skills and ability to work in a large team. "Nice To Have" Skills and Experience Experience with both UVM & formal verification Experience working with project management and leads on planning tasks, setting schedules, and quality checkpoints. Experience mentoring team members or reviewing other's technical work. Knowledge of scripting (e.g. Python, Perl or Unix shell scripting More ❯