Senior Engineer
- Hiring Organisation
- ARM
- Location
- Cambridge, Cambridgeshire, United Kingdom
- Salary
- £ 70 K
blocks based on architecture and build specificationsBuild and implement SystemVerilog/UVM-based verification environments, including testbenches, stimulus, and checkersDefine functional and code coverage goals and drive coverage closureDebug RTL and verification issues, working closely with build and architecture teams to resolve problemsComplete regression testing and analyze … including development of constrained-random environmentsStrong proficiency in SystemVerilog and familiarity with UVM or similar methodologiesExperience in writing test plans, developing testbenches, and driving coverage closureGood debugging and problem-solving skills in complex simulation environmentsUnderstanding of verification fundamentals, including functional coverage and assertionsExperience with scripting languages (e.g., Python ...