2 of 2 Remote/Hybrid UVM Jobs in the East of England

system-level designs including RISC-V cores, cryptographic IP (OTBN), and key peripherals (USB, I2C, SPI). Key Responsibilities Develop and debug SystemVerilog/UVM testbenches Create verification plans, tests, and coverage Review contributions and resolve regressions Support CI/test infrastructure Collaborate with partners through tapeout Requirements 5+ years … industry verification experience Strong SystemVerilog and UVM Full verification lifecycle experience through tapeout C and/or Python for automation Git/GitHub collaboration Desirable: Formal verification (Jasper), RISC-V/ISA knowledge, security verification, silicon bring-up, or technical leadership experience. ...

level designs including RISC-V cores, cryptographic IP (OTBN), and key peripherals (USB, I2C, SPI). xkybehq Key Responsibilities Develop and debug SystemVerilog/UVM testbenches Create verification plans, tests, and coverage Review contributions and resolve regressions Support CI/test infrastructure Collaborate with partners through tapeout Requirements 5+ years … industry verification experience Strong SystemVerilog and UVM Full verification lifecycle experience through tapeout C and/or Python for automation Git/GitHub collaboration Desirable: Formal verification (Jasper), RISC-V/ISA knowledge, security verification, silicon bring-up, or technical leadership experience. ...