Senior or Principal Firmware / FPGA Engineer
- Hiring Organisation
- Leonardo DRS
- Location
- Edinburgh, Midlothian, United Kingdom
- Salary
- £ 50 K
Verilog an advantage but not essential. Implementing high speed, multi-frequency clocking architecturesDesign with FPGA technologies from either AMD(Xilinx), Intel (Altera) or Microsemi (Actel).Use of Xilinx Vivado or Altera Quartus II/Quartus Prime is an advantageExperience of FPGA architectures such as SoC system-on-chip (e.g. ...