2 of 2 Remote/Hybrid SystemVerilog Jobs in Edinburgh

/Computer Science or other related discipline. Metric driven verification – verification planning, requirements extraction – directed and constrained random verification – functional and code coverage analysis SystemVerilog – SVA (SystemVerilog Assertions) Testbench design with verification frameworks like UVM/OVM, e, VMM Debugging skills – RTL – Testbench, OOP – Gate level (including SDF) Scripting experience ...

delivering first-time success with complex mixed-signal ICs Metric-driven verification: planning, requirements extraction, directed & constrained-random verification, functional and code coverage analysis SystemVerilog, including SVA (SystemVerilog Assertions) Testbench design using verification frameworks such as UVM, OVM, e, or VMM Strong RTL/testbench debugging skills (including gate-level ...