5 of 5 Remote/Hybrid ASIC Design Engineer Jobs in England

Digital ASIC Design Engineer

Hiring Organisation
Technical Futures Ltd
Location
Cambridge, Cambridgeshire, United Kingdom
Employment Type
Permanent
Digital ASIC Design Engineer seeking a challenging career move where you can contribute to the very latest imaging and augmented reality systems, designing and implementing FPGA based SoC systems? Hybrid working (up to 3 days per week from home) and very generous salary on offer. Applications welcome … from mid to senior level engineers. This award-winning Technology company seeks a Degree qualified Digital ASIC Design Engineer with SoC design and Integration skills, proven FPGA, VHDL & Verilog experience, RTL Verification experience and some Python knowledge. In this role the successful Digital ASIC Design ...

Senior Digital ASIC/SoC Design Engineer (Hybrid)

Location
Cambridge, England, United Kingdom
Technical Futures Ltd in Cambridge is seeking a Digital ASIC Design Engineer to design and implement FPGA-based SoC systems. Hybrid working (up to 3 days per week from home) and a very generous salary on offer. Applications welcome from mid to senior level engineers with … strong VHDL/Verilog, RTL verification and Python skills, plus experience in SoC design and integration. You will work closely with hardware, software and mechanical teams to bring new imaging/AR products to market. #J-18808-Ljbffr ...

Senior Digital Design Engineer (Hybrid) ASIC Frontend Lead

Location
Greater London, England, United Kingdom
MintNeuro in London seeks a Senior Digital Design Engineer to own front-end digital design and verification for next-generation mixed-signal ASICs used in implantable neural interfaces. You will write clean Verilog/SystemVerilog, develop robust verification environments, drive RTL from concept to tape ...

Remote Senior Physical Design & STA Engineer (5nm ASICs)

Location
Greater London, England, United Kingdom
Swedium Global Services is seeking a Senior Physical Design Engineer (remote from the UK/EU) to drive timing closure for ASIC/SoC designs across advanced nodes, including <5nm processes. You will work closely with PD, RTL, Synthesis, and Signoff teams to resolve timing and clock … related challenges. The role requires 5+ years in Physical Design/STA, strong experience with Synopsys or Cadence tools, and hands-on knowledge of SDC, PVT corners, and timing ECOs. Remote work from the UK/EU is supported. #J-18808-Ljbffr ...

Senior Design Engineer – Hybrid (FPGA/ASIC)

Location
West of England, England, United Kingdom
AccelerComm Ltd in Bristol is seeking Senior Design Engineers to work on space-qualified 5G base station technology for satellite deployment. You will deliver RTL designs for ASIC/FPGA, collaborate across architecture, verification, and implementation teams, and deploy on FPGA platforms. The role involves working with ...