5 of 5 Remote/Hybrid UVM Jobs in England

Principal and Lead FPGA Engineers

Hiring Organisation
17918
Location
Luton, Bedfordshire, United Kingdom
just have lots of skills and experience gained through your hard work. Design tools such as Xilinx, TCL, Verilog, System Verilog and UVM FPGA architectures such as Xilinx 7. Xilinx UltraScale; Intel (Altera) or Microsemi (Actel). Fast interfaces such as PCIe, Ethernet, and JESD is also required. Auto-generated ...

FPGA Designer

Hiring Organisation
MBDA UK
Location
Bristol, Filton, Gloucestershire, United Kingdom
Employment Type
Permanent
Salary
£75000/annum
design implementations using VHDL, Simulink, etc., targeting Xilinx, Intel, and Microsemi devices. Ability to verify complex FPGA implementations using VHDL and System Verilog/UVM test-bench methodologies. Proficiency in FPGA design toolsets and Mentor verification tools (QuestaSim & ModelSim). Strong skills in generating low-level software (C) for FPGA ...

FPGA Firmware Engineer - Hybrid (Airborne EO Systems)

Hiring Organisation
Jobleads-UK
Location
Basildon, England, United Kingdom
Job Description At Leonardo, we are excited to be recruiting for a skilled FPGA Engineer to work within a multi-disciplinary team for our Precision Guidance area. In this broad FPGA firmware engineering role, you ...

Digital Verification Engineer

Hiring Organisation
Microtech Global Ltd
Location
Cambridge, Cambridgeshire, East Anglia, United Kingdom
Employment Type
Permanent, Work From Home
experienced engineers, helping to develop robust verification environments while gaining exposure to production silicon and advanced verification methodologies. Responsibilities Develop and debug SystemVerilog/UVM testbenches. Create and execute verification plans, tests, and coverage. Debug simulation failures and support regression testing. Contribute to verification infrastructure and automation. Collaborate closely with ...

Principal Verification Engineer Jobs in UK 2026

Hiring Organisation
Jobleads-UK
Location
Bristol, England, United Kingdom
performance, and engineering best practices. Job Requirements Extensive experience with constrained-random verification and ownership of complex verification environments. Strong expertise in SystemVerilog and UVM (SV-UVM) for developing scalable verification code and testbenches. Proficiency in scripting to support verification workflows and automation. Strong software engineering knowledge, including object-oriented ...