10 of 10 Remote/Hybrid SystemVerilog Jobs in Midlothian

development stage): Hardware requirements, capture and management Concept development for complex functions and systems FPGA design, implementation, and analysis Applying verification techniques usingVHDL or SystemVerilog, with exposure toUVMwhere applicable Production of material for design reviews Development of test planning, integration, and design verification activities Ensuring all firmware designs comply with ...

Depending on your experience, youll bring some, or all, of the following: Experience in design techniques using VHDL Experience in verification techniques using eitherVHDLor SystemVerilog/UVM. Experience in specifying timing and area constraints forefficientFPGA place and route. Ability toanalysesystem level requirements and derive detailedfirmwarerequirements. Degree (BSc, BEng, MEng ...

discipline) with an extensive proven background in digital CMOS circuit design Implementation of complex digital circuits and sub-systems in RTL using Verilog/SystemVerilog Understanding of digital system-level design, including use of standard bus protocols, bus architecture design and chip-level clock and reset architectures Verification of block ...

success with complex mixed signal IC’s.Metric driven verification - verification planning, requirements extraction - Directed and constrained random verification - Functional and code coverage analysisSystemVerilog - SVA (SystemVerilog Assertions)Testbench design with verification frameworks like UVM/OVM, e, VMMDebugging skills - RTL - Testbench, OOP - Gate level (including SDF)Strong ability to interpret results ...

problem solver.Preferred Skills and Qualifications: Scripting experience with Python, sh/csh, TCL, MakeObject orientated programming (OOP) - Use of OOP design patternsKnowledge of SVA (SystemVerilog Assertions)Metric driven verification - verification planning, requirements extraction - Directed and constrained random verificationFunctional and code coverage analysisPower aware verification (using CPF/UPF)Testbench design ...

Bachelor’s, Master's or PhD degree in Electrical Engineering (or related discipline) Comprehensive understanding of digital circuit design in RTL using Verilog and SystemVerilog Knowledge and understanding of verification of block-level digital designs Experience and understanding of synthesis and timing analysis of digital circuits Knowledge of design ...

Job Description:Salary: 60,000 to 84,955Leonardo UK operates a grade-based salary framework with broad bands. The salary range shown reflects the approved grade band for this role, or a narrower hiring range ...

Job Description:Salary: Engineer: 37,400 to 53,550/Senior: 45, 200 to 61,950/Principal: 53,300 to 71,400/Lead: 59,400 to 84,955Leonardo UK operates a grade-based ...

other verification engineers to deliver high-quality silicon solutions.ResponsibilitiesDevelop and execute comprehensive verification plans for complex mixed-signal ASIC designs.Create and maintain testbenches using SystemVerilog/UVM.Write and debug test cases to verify functionality, performance, and corner cases.Perform block-level and full-chip verification, including simulation, coverage analysis, and regression … degree in Electrical Engineering, Computer Engineering, or related field.10+ years of experience in digital and/or mixed-signal design verification.Strong proficiency in SystemVerilog, UVM, and simulation tools (Synopsys VCS, Cadence Xcelium).Solid understanding of digital design fundamentals, RTL design, and ASIC development flows.Experience with scripting languages (Python, Perl ...

development lifecycle. This is a hands-on verification role covering everything from planning and testbench development through to coverage closure and debugging. Responsibilities Develop SystemVerilog and UVM verification environments Create reusable verification components and testbenches Write assertions and functional coverage Debug complex RTL and simulation issues Drive verification activities from … sign-off Work closely with cross-functional engineering teams Help improve verification methodology and best practice About You You'll ideally have experience with: SystemVerilog UVM ASIC or SoC Verification Functional Coverage SystemVerilog Assertions (SVA) RTL Debug Verification Planning Experience within automotive or safety-critical semiconductor development would be beneficial ...