6 of 6 Remote Python Jobs in Northern Ireland

short: Tech Lead/Engineering Lead experience – leading pods of around 3–6 engineers Strong, recent hands-on coding in .NET, Java, or Python (not just oversight) Deep experience in cloud architecture and infrastructure , (AWS or Azure, Terraform, Kubernetes, CI/CD) Proven ability to re-architect or modernise platforms ...

. Collaboration with global engineering teams is central to this role. Key Skills Required Embedded software development in C/C++ , plus scripting with Python and Bash Strong experience with bare-metal , Yocto Linux , Zephyr , RTOS SoC software flows , co-simulation, hardware debug and board bring-up High-speed interface ...

role focuses on high-speed digital interfaces such as 100Gb Ethernet, PCIe Gen5, AXI/AMBA , and requires strong expertise in Vivado, Vitis, Python, Tcl, Git and CI/CD workflows . Key Responsibilities Design high-performance IP using SystemVerilog RTL for FPGA/Adaptive SoC Deliver synthesis-ready … integration requirements Implement and optimise 100GbE, PCIe Gen5, AXI/AMBA IP blocks Drive timing closure using Vivado toolchains Develop automation using Python/Tcl scripting Collaborate with hardware, SoC, firmware and integration teams Essential Skills Strong SystemVerilog RTL design experience FPGA/Adaptive SoC design flow: synthesis ...

role focuses on high-speed digital interfaces such as 100Gb Ethernet, PCIe Gen5, AXI/AMBA , and requires strong expertise in Vivado, Vitis, Python, Tcl, Git and CI/CD workflows . Key Responsibilities Design high-performance IP using SystemVerilog RTL for FPGA/Adaptive SoC Deliver synthesis-ready … integration requirements Implement and optimise 100GbE, PCIe Gen5, AXI/AMBA IP blocks Drive timing closure using Vivado toolchains Develop automation using Python/Tcl scripting Collaborate with hardware, SoC, firmware and integration teams Essential Skills Strong SystemVerilog RTL design experience FPGA/Adaptive SoC design flow: synthesis ...

/RF signal-chain blocks including FFT, FIR filters and channelizers Integrate VIP and drive constrained-random and coverage-driven verification Automate regressions using Python scripting Work within CI/CD environments and version control using Git Support ASIC/SoC/FPGA verification flows Essential Skills & Experience Strong experience … Verification Engineer/ASIC Verification Engineer Proven UVM and class-based verification expertise Solid background in DSP verification (FFT, FIR, signal processing) Python for automation and regression Experience with SoC/ASIC/FPGA environments Git version control Desirable MATLAB experience Exposure to Vivado/Vitis or adaptive SoC flows ...

/RF signal-chain blocks including FFT, FIR filters and channelizers Integrate VIP and drive constrained-random and coverage-driven verification Automate regressions using Python scripting Work within CI/CD environments and version control using Git Support ASIC/SoC/FPGA verification flows Essential Skills & Experience Strong experience … Verification Engineer/ASIC Verification Engineer Proven UVM and class-based verification expertise Solid background in DSP verification (FFT, FIR, signal processing) Python for automation and regression Experience with SoC/ASIC/FPGA environments Git version control Desirable MATLAB experience Exposure to Vivado/Vitis or adaptive SoC flows ...