5 of 5 Remote/Hybrid SystemVerilog Jobs in Oxfordshire

FPGA-based signal processing techniques including DDC/DUC, DDS, and FIR/IIR filters, as well as strong experience in FPGA verification and SystemVerilog development. We're looking for someone who is fluent in modelling and simulation using Python and/or MATLAB/Simulink, with practical experience ...

Collaborate with multidisciplinary teams to deliver next-generation quantum technologies. What We’re Looking For: Strong experience in FPGA programming (VHDL/Verilog/SystemVerilog) and DSP implementation. Knowledge of digital and RF hardware, with hands-on experience in embedded systems. Experience with standard hardware interfaces (I2C, SPI, UART ...

will lead the design and verification of FPGA test benches and contribute to robust control systems for quantum hardware. You will own verification environments (SystemVerilog/UVM), drive constrained‐random testing and coverage, and help shape automated regression and CI pipelines. Hybrid work and competitive compensation are offered. #J ...

develop critical simulation infrastructure, contributing directly to the success of the FPGA team. Key responsibilities include: Architect, develop, and maintain advanced UVM/SystemVerilog verification environments for complex FPGA designs. Define and execute comprehensive verification plans, including constrained-random testing, functional coverage, and code coverage analysis. Collaborate with RTL design … robust verification strategies, and work collaboratively across design teams to ensure high-quality outcomes. You'd be a great fit with: Strong proficiency in SystemVerilog and UVM for architecting advanced verification environments. Experience using Python for test automation and scripting. Demonstrated ability to lead requirements gathering and define verification plans ...

develop critical simulation infrastructure, contributing directly to the success of the FPGA team. Key responsibilities include Architect, develop, and maintain advanced UVM/SystemVerilog verification environments for complex FPGA designs. Define and execute comprehensive verification plans, including constrained‐random testing, functional coverage, and code coverage analysis. Collaborate with RTL design … robust verification strategies, and work collaboratively across design teams to ensure high‐quality outcomes. You'd be a great fit with Strong proficiency in SystemVerilog and UVM for architecting advanced verification environments. Experience using Python for test automation and scripting. Demonstrated ability to lead requirements gathering and define verification plans ...