7 of 7 Remote UVM Jobs in Scotland

verification planning, requirements extraction – directed and constrained random verification – functional and code coverage analysis SystemVerilog – SVA (SystemVerilog Assertions) Testbench design with verification frameworks like UVM/OVM, e, VMM Debugging skills – RTL – Testbench, OOP – Gate level (including SDF) Scripting experience with Ruby, sh/csh, TCL, Make, Perl Power aware ...

verification planning, requirements extraction – directed and constrained random verification – functional and code coverage analysis SystemVerilog – SVA (SystemVerilog Assertions) Testbench design with verification frameworks like UVM/OVM, e, VMM Debugging skills – RTL – Testbench, OOP – Gate level (including SDF) Scripting experience with Ruby, sh/csh, TCL, Make, Perl Power aware ...

verification planning, requirements extraction – directed and constrained random verification – functional and code coverage analysis SystemVerilog – SVA (SystemVerilog Assertions) Testbench design with verification frameworks like UVM/OVM, e, VMM Debugging skills – RTL – Testbench, OOP – Gate level (including SDF) Scripting experience with Ruby, sh/csh, TCL, Make, Perl Power aware ...

verification planning, requirements extraction – directed and constrained random verification – functional and code coverage analysis SystemVerilog – SVA (SystemVerilog Assertions) Testbench design with verification frameworks like UVM/OVM, e, VMM Debugging skills – RTL – Testbench, OOP – Gate level (including SDF) Scripting experience with Ruby, sh/csh, TCL, Make, Perl Power aware ...

tape-out, including performance review, analysis, costing, and optimisation Understanding of the product's design & verification needs, standardisation, adherence to frameworks and methodolgies e.g. UVM Excellent communicator, with a keen interest in team collaboration and a clear approach to the design & development process Bonus/"Nice-to-have" skills Digital ...

tape-out, including performance review, analysis, costing, and optimisation Understanding of the product's design & verification needs, standardisation, adherence to frameworks and methodolgies e.g. UVM Excellent communicator, with a keen interest in team collaboration and a clear approach to the design & development process Bonus/"Nice-to-have" skills Digital ...

signal ASIC designs using advanced verification methodologies. Key responsibilities Develop and execute comprehensive verification plans for complex mixed-signal ASIC designs Create and maintain UVM-based SystemVerilog testbenches. Write, debug, and execute test cases to verify functionality, performance, and corner cases Perform block-level and full-chip verification, including simulation … improvement of design and verification best practices Qualifications 5+ years’ experience in digital and/or mixed-signal design verification Strong proficiency in SystemVerilog, UVM, and leading simulation tools (e.g., Synopsys VCS, Cadence Xcelium) Solid understanding of digital design principles, RTL design, and ASIC development flows Experience with scripting languages ...