requirements. Responsibilities Design tools such as Xilinx, TCL, Verilog, System Verilog and UVM FPGA architectures such as Xilinx 7. Xilinx UltraScale; Intel (Altera) or Microsemi (Actel). Fast interfaces such as PCIe, Ethernet, and JESD is also required. Auto-generated code using model driven engineering using Matlab and Simulink More ❯
to protect personnel from threats like Improvised Explosive Devices (IEDs) in both military and civilian environments. Essential: Using FPGA technologies especially from either Xilinx, Microsemi (Actel) or Lattice and their tools Advanced verification techniques using either VHDL or System Verilog/UVM Specifying complex timing and area constraints for More ❯
design, coding, debugging, reviewing and testing complex digital high speed systems Proficient in digital implementation in VHDL language Familiar with Xilinx (AMD) Vivado and Microsemi Libero design tools, Block Diagram Design entry as well as VHDL, & IP integrator. Proficient in designing digital processing components and algorithms in Matlab/ More ❯
in designing embedded Linux drivers for custom programmable logic firmware interfaces Experience with memory management using DDR, DMA, cache coherency, and partitioning Experience with MicroSemi Smartfusion2 devices and designing embedded applications running on FreeRTOS on its ARM Cortex M3 processor Experience with UML Modelling and documentation Proficiency in verification More ❯
Firmware Engineer: Experienced with Mentor Graphics FPGA development tools including HDL Designer, ModelSim/Questa and Precision Familiar with Xilinx/Intel (Altera)/Microsemi (Actel) design flows (ISE, Vivado, Quartus) and third-party synthesis tools Experience in specifying timing and area constraints for efficient FPGA Place and Route. … verification methodologies Experienced with Mentor Graphics FPGA development tools including HDL Designer, ModelSim/Questa and Precision Familiar with Xilinx/Intel (Altera)/Microsemi (Actel) design flows (ISE, Vivado, Quartus) and third-party synthesis tools Experience in specifying timing and area constraints for efficient FPGA Place and Route. More ❯
