5 of 5 Remote/Hybrid UVM Jobs in the South East

design and verification of FPGA test benches and contribute to robust control systems for quantum hardware. You will own verification environments (SystemVerilog/UVM), drive constrained‐random testing and coverage, and help shape automated regression and CI pipelines. Hybrid work and competitive compensation are offered. #J-18808-Ljbffr ...

## VHDL FPGA Firmware EngineerApplylocations: GB - Southampton: GB - Bristol - Coldharbour Lanetime type: Full timeposted on: Posted Todayjob requisition id: R0026952**Job Description:****Salary Ranges**Engineer: £38k - £53kSenior: £45k - £61kLeonardo UK operates a grade-based salary ...

algorithms, working across IP development, integration and verification. To support this work, we are looking for a Senior Verification Engineer to support the complete UVM verification of Accelercomm IP. Responsible for verification of RTL implementations for advanced wireless communications IP and modem subsystems, ensuring designs meet functional, performance and quality … requirements prior to FPGA deployment and ASIC tape-out. Key Responsibilities Develop verification plans from design and architecture specifications. Create and maintain SystemVerilog/UVM verification environments. Develop testbenches, assertions, scoreboards and coverage models. Execute directed and constrained-random verification. Analyse coverage and debug RTL and verification issues. Support subsystem ...

architect, and develop critical simulation infrastructure, contributing directly to the success of the FPGA team. Key responsibilities include Architect, develop, and maintain advanced UVM/SystemVerilog verification environments for complex FPGA designs. Define and execute comprehensive verification plans, including constrained‐random testing, functional coverage, and code coverage analysis. Collaborate with … strategies, and work collaboratively across design teams to ensure high‐quality outcomes. You'd be a great fit with Strong proficiency in SystemVerilog and UVM for architecting advanced verification environments. Experience using Python for test automation and scripting. Demonstrated ability to lead requirements gathering and define verification plans for complex ...

seeks a Senior Verification Engineer to drive full lifecycle verification of RTL IP across ASIC/FPGA; you will develop verification plans, create UVM testbenches and support integration and tape-out readiness. Requirements include 3+ years in digital verification, strong SystemVerilog/UVM, Linux scripting and a collaborative mindset. Hybrid ...