1 of 1 Remote/Hybrid SystemVerilog Jobs in South Wales

ASIC Design Engineer

Hiring Organisation
Intellectual Capital Resources
Location
Cardiff, UK
trust What you’ll be doing Define digital architectures for AI accelerators, data paths, and SoC subsystems Develop high-quality, synthesizable RTL (Verilog/SystemVerilog). Run synthesis, STA, and DFT using industry-standard digital design tools Lead design reviews and help establish best practices and design flows Support tapeout ...