2 of 2 Code Coverage Jobs in the Thames Valley

develop, and maintain advanced UVM/SystemVerilog verification environments for complex FPGA designs. Define and execute comprehensive verification plans, including constrained‐random testing, functional coverage, and code coverage analysis. Collaborate with RTL design engineers to debug issues, identify root causes, and ensure high-quality design implementation. Develop ...

digital subsystems and mixed-signal ICs. Your work will include: Developing SystemVerilog/UVM verification environments Verification planning and test development Constrained-random and coverage-driven verification SVA/assertions Functional and code coverage RTL and testbench debugging Verification methodology and infrastructure improvements Working closely with design … ideally have a background in ASIC, SoC or Digital IC Verification, with strong experience in: SystemVerilog | UVM | SVA | Constrained Random Verification | Functional Coverage | RTL Debug Experience with mixed-signal verification, formal verification, UPF/low-power verification, gate-level simulation or scripting would be particularly valuable. Why consider ...