11 of 11 Remote Verilog Jobs in the UK

other high-integrity engineering domains. Strong communication skills and ability to work within structured engineering processes. Technical Knowledge Beneficial to the Role VHDL , Verilog or SystemVerilog for digital design and implementation. Verification testbench architecture using SystemVerilog or C++ . Advanced verification methodologies such as OSVVM , UVVM or advanced VHDL verification ...

architectures and design implementations using VHDL, Simulink, etc., targeting Xilinx, Intel, and Microsemi devices. Ability to verify complex FPGA implementations using VHDL and System Verilog/UVM test-bench methodologies. Proficiency in FPGA design toolsets and Mentor verification tools (QuestaSim & ModelSim). Strong skills in generating low-level software ...

architectures and design implementations using VHDL, Simulink, etc., targeting Xilinx, Intel, and Microsemi devices. Ability to verify complex FPGA implementations using VHDL and System Verilog/UVM test-bench methodologies. Proficiency in FPGA design toolsets and Mentor verification tools (QuestaSim & ModelSim). Strong skills in generating low-level software ...

architectures and design implementations using VHDL, Simulink, etc., targeting Xilinx, Intel, and Microsemi devices. Ability to verify complex FPGA implementations using VHDL and System Verilog/UVM test-bench methodologies. Proficiency in FPGA design toolsets and Mentor verification tools (QuestaSim & ModelSim). Strong skills in generating low-level software ...

BEng or MEng in Engineering, Electronics, or related subjects (upper second class or equivalent) Extensive post-graduate engineering experience Desirable: Knowledge of SPICE, HDL, Verilog, or FPGA Experience with physics modelling tools such as Ansys/HFSS Previous HMI or display industry experience What You Can Expect My client offers ...

FPGA architecture design Experience with DSP design and signal processing (RF, ADCs, DACs) Hands-on digital logic design at RTL level VHDL or Verilog exposure in a commercial environment Experience with Xilinx toolchains is a bonus (Vivado, Vitis, Petalinux ...

FPGA architecture design Experience with DSP design and signal processing (RF, ADCs, DACs) Hands-on digital logic design at RTL level VHDL or Verilog exposure in a commercial environment Experience with Xilinx toolchains is a bonus (Vivado, Vitis, Petalinux JBRP1_UKTJ ...

FPGA or digital hardware design experience, including 3-5 years in a leadership/management role Strong experience with RTL design (VHDL/Verilog/SystemVerilog), simulation, synthesis, timing analysis, and hardware validation Knowledge of high-speed interfaces, DSP, control logic, and Image Processing Understanding of hardware-software co-design ...

Qualifications: Bachelor's, Master's or PhD degree in Electrical Engineering (or related discipline) Comprehensive understanding of digital circuit design in RTL using Verilog and SystemVerilog Knowledge and understanding of verification of block-level digital designs Experience and understanding of synthesis and timing analysis of digital circuits Knowledge of design ...

support your professional growth in a diverse, inclusive environment. Key Responsibilities: Design high-performance IP targeting FPGA/Adaptive SoC technology using System Verilog RTL. Deliver synthesis-ready designs that meet timing and integration requirements. Collaborate with engineering teams to ensure quality and performance targets are met. Skills, Experience … Abilities Required: Expertise in System Verilog RTL design Hands-on experience with 100Gb Ethernet, PCIe Gen5, AMBA/AXI In-depth knowledge of FPGA/Adaptive SoC design flow, including place & route (P&R) and timing closure Proficiency in Vivado/Vitis Strong scripting skills in Python and Tcl Experience ...

through your own PSC To be considered for this role, candidates must possess the following skills and experience: - Proven experience in RTL development using Verilog/System Verilog - Demonstrated expertise in digital IC design and verification - Proficiency in digital IC backend flow synthesis This role is ideal for a Contract ...