8 of 8 Permanent SystemVerilog Jobs in Cambridge

create test plans for highly configurable IPs meant to provide interconnectivity between components across an SOC, chiplet or multi chiplet systems Write UVM/SystemVerilog code to implement the test plan, checkers and scoreboards Collaborate with software teams to define and implement configurable testbenches Work with design and DV engineers … Engineering or Computer Science 8+ years and current hands-on experience in block-level/IP-level/SOC-level verification Proficiency in Verilog, SystemVerilog Familiarity with industry-standard EDA tools for simulation and debug Deep experience with UVM-based testbenches Experience with modern programming languages like Python Knowledge ...

/GPU design techniques and tools What we’re looking for Essential Strong background in digital IC design methodologies Hands-on RTL design experience (SystemVerilog) at IP or SoC level Experience optimising designs for performance-critical silicon Familiarity with ASIC and/or FPGA design flows Strong analytical mindset ...

Design Verification Engineer This is a superb opportunity to join one of the hottest names in the industry! A chance to build a technology that transforms the future of humanity. A chance to work on ...

Physics or similar A-Levels in Mathematics, Physics or similar graded A* - B Proficiency in C, C++, Python Desired: experience with HDLs such as SystemVerilog or VHDL If you are an PhD graduate looking for an exciting Software Engineer opportunity to work at the intersection of software, hardware, and research ...

edge sign-off methodologies. Key requirements: Mastery of industry-standard formal tools (e.g., JasperGold, VC Formal, or Questa Formal). Hands-on expertise writing SystemVerilog Assertions. PExperience in deep bug-hunting, coverage closure, and achieving formal sign-off on complex IPs. Knowledge of GPU architectures or sequential equivalence checking ...

open-source digital designs, including OpenTitan, RISC-V cores, OTBN, crypto accelerators, and peripherals . What Youll Do: Lead design, implementation, and debugging of SystemVerilog/UVM testbenches Develop verification plans, tests, and coverage xkybehq strategies Mentor engineers and drive best practic Please ensure you read the below overview ...

designs including OpenTitan , RISC-V cores, cryptographic CPUs (OTBN), crypto accelerators, and peripherals such as USB, I2C, and SPI. Responsibilities Design, implement, and debug SystemVerilog/UVM testbenches Develop verification plans, tests, and coverage Review open-source contributions and debug regressions Contribute to test and CI infrastructure Collaborate with partners … support successful tapeouts Requirements Essential 5 years industry experience xkybehq in design verification Strong SystemVerilog and UVM experience Full verification lifecycle experience through tapeout C and/or Python for tests and automation Git/GitHub and collaborative team experience Desirable Formal verification (e.g. Jasper) RISC-V or ISA experience ...

designs including OpenTitan , RISC-V cores, cryptographic CPUs (OTBN), crypto accelerators, and peripherals such as USB, I2C, and SPI. Responsibilities Design, implement, and debug SystemVerilog/UVM testbenches Develop verification plans, tests, and coverage Review open-source contributions and debug regressions Contribute to test and CI infrastructure Collaborate with partners … support successful tapeouts Requirements Essential 5+ years industry experience in design verification Strong SystemVerilog and UVM experience Full verification lifecycle experience through tapeout C and/or Python for tests and automation Git/GitHub and collaborative team experience Desirable Formal verification (e.g. Jasper) RISC-V or ISA experience Security ...