18 of 18 Permanent SystemVerilog Jobs in the East of England

engineering experience (implementation, simulation, verification and test) Strong background in Digital Signal Processing (DSP) design and optimisation Excellent academic background with a degree from a top university Proficiency in SystemVerilog or VHDL Experience with high-speed external interfaces (e.g. PCIe, Aurora, Ethernet, SPI) Proven ability to take technical ownership, collaborate effectively, and deliver complex projects Position: Senior FPGA Engineer Location More ❯

as SPI, I2C, UART, GPIO, Raspberry Pi, Test automation scripting languages – Python, TCL to 10 years of experience Strong experience in CPLD/FPGA firmware development using Verilog/SystemVerilog Proficiency in scripting languages (e.g., Python, TCL) for automation and debug Hands-on experience with FPGA and Raspberry Pi integration Ability to create and maintain detailed technical documentation (TRMs, register More ❯

as SPI, I2C, UART, GPIO, Raspberry Pi, Test automation scripting languages – Python, TCL to 10 years of experience Strong experience in CPLD/FPGA firmware development using Verilog/SystemVerilog Proficiency in scripting languages (e.g., Python, TCL) for automation and debug Hands-on experience with FPGA and Raspberry Pi integration Ability to create and maintain detailed technical documentation (TRMs, register More ❯

engineering experience (implementation, simulation, verification and test) Strong background in Digital Signal Processing (DSP) design and optimisation Excellent academic background with a degree from a top university Proficiency in SystemVerilog or VHDL Proven ability to take technical ownership, collaborate effectively, and deliver complex projects Position: Senior FPGA Engineer Location: Cambridge Salary: £70k–£120k + equity Key Skills: FPGA, DSP, Verilog More ❯

deliver high-performance solutions Stay at the forefront of FPGA technology and help shape our roadmap What we're looking for Strong FPGA design background (VHDL/Verilog/SystemVerilog) Experience leading or mentoring engineering teams Proven delivery of complex FPGA systems Solid grasp of RTL design, timing closure, verification, and integration Confident communicator who thrives on problem-solving and More ❯

not just depth: the digital cores are the nexus of these mixed-signal chips, tying everything together. ?? What youll be doing End-to-end RTL design using Verilog/SystemVerilog Designing synchronous and asynchronous state machines and control logic Working on analog/digital partitioning and functional modelling FPGA emulation, lab validation, post-design analysis, and place & route support Collaborating More ❯

. 8+ years of hands-on experience in microarchitecture and RTL design. Proven experience as a team or technical lead within ASIC/SoC projects. Proficiency in Verilog and SystemVerilog . Strong knowledge of EDA tools and flows . In-depth expertise with on-chip interconnects and NoCs . Experience designing cache/memory subsystems, interconnects, or NoCs is a More ❯

. 8+ years of hands-on experience in microarchitecture and RTL design. Proven experience as a team or technical lead within ASIC/SoC projects. Proficiency in Verilog and SystemVerilog . Strong knowledge of EDA tools and flows . In-depth expertise with on-chip interconnects and NoCs . Experience designing cache/memory subsystems, interconnects, or NoCs is a More ❯

Working for a cutting edge semiconductor company, I have a high-profile role available, as Chief Architect/Chief NPU Architect. You will be part of key R&D projects for complex CPU/NPU/GPU related architecture requirements More ❯

Working for a cutting edge semiconductor company, I have a high-profile role available, as Chief Architect/Chief NPU Architect. You will be part of key R&D projects for complex CPU/NPU/GPU related architecture requirements More ❯

Working for a cutting edge semiconductor company, I have a high-profile role available, as Chief Architect/Chief NPU Architect. You will be part of key R&D projects for complex CPU/NPU/GPU related architecture requirements More ❯

RISC-V cores, OTBN (cryptographic CPU), AES accelerators, and peripherals like USB, I2C, and SPI. Key Responsibilities Design, implement, and debug block/system-level tests and testbenches using SystemVerilog and UVM Develop test and coverage plans for new and updated designs Triage and debug nightly regressions Review contributions to open-source projects Enhance test and CI infrastructure Collaborate on … academic/industry publications Stay current with verification best practices and introduce improvements Candidate Requirements Essential: 5+ years industry experience in design verification Strong SystemVerilog and UVM expertise Experience across the full verification cycle (planning to tape-out) Able to provide estimates and coordinate with project managers Comfortable in multidisciplinary, multi-organisation teams Familiar with Git and code review tools More ❯

to innovative hardware solutions. Responsibilities : Create test plans for highly configurable IPs meant to provide interconnectivity between components across an SoC, chiplet, or multi-chiplet systems Write UVM/SystemVerilog code to implement the test plan, checkers, and scoreboards Collaborate with software teams to define and implement configurable testbenches Work with design teams test plans, failure debug, coverage, etc. Qualifications … MS in Electrical Engineering, Computer Engineering or Computer Science 6+ years and current hands-on experience in block-level/IP-level/SoC-level verification Proficiency in Verilog, SystemVerilog Deep experience with UVM-based testbenches Knowledge of Arm AMBA protocols such as AXI, APB, and AHB Understanding of Arm CHI protocol is a plus Experience on working with IP More ❯

to innovative hardware solutions. Responsibilities : Create test plans for highly configurable IPs meant to provide interconnectivity between components across an SoC, chiplet, or multi-chiplet systems Write UVM/SystemVerilog code to implement the test plan, checkers, and scoreboards Collaborate with software teams to define and implement configurable testbenches Work with design teams test plans, failure debug, coverage, etc. Qualifications … MS in Electrical Engineering, Computer Engineering or Computer Science 6+ years and current hands-on experience in block-level/IP-level/SoC-level verification Proficiency in Verilog, SystemVerilog Deep experience with UVM-based testbenches Knowledge of Arm AMBA protocols such as AXI, APB, and AHB Understanding of Arm CHI protocol is a plus Experience on working with IP More ❯

in every design you deliver. What you’ll do Work closely with hardware designers and system architects to define and own verification plans based on design specifications Develop scalable SystemVerilog testbenches , including checkers, coverage groups, and reference models Design and run self-checking, directed, and randomized tests Maintain the verification environment, including tracking regressions, bugs, and coverage metrics Drive quality … level designs Core skills Strong commercial experience in functional verification , with ownership of verification strategy and planning Expertise in testbench design using frameworks like UVM or OVM Proficiency with SystemVerilog assertions (SVA) Familiarity with multiple programming languages (e.g., C, C++, Python ) Visa sponsorship will be provided for candidates who require. Please note, you must already be living and working in More ❯

in every design you deliver. What you’ll do Work closely with hardware designers and system architects to define and own verification plans based on design specifications Develop scalable SystemVerilog testbenches , including checkers, coverage groups, and reference models Design and run self-checking, directed, and randomized tests Maintain the verification environment, including tracking regressions, bugs, and coverage metrics Drive quality … level designs Core skills Strong commercial experience in functional verification , with ownership of verification strategy and planning Expertise in testbench design using frameworks like UVM or OVM Proficiency with SystemVerilog assertions (SVA) Familiarity with multiple programming languages (e.g., C, C++, Python ) Visa sponsorship will be provided for candidates who require. Please note, you must already be living and working in More ❯

in every design you deliver. What you’ll do Work closely with hardware designers and system architects to define and own verification plans based on design specifications Develop scalable SystemVerilog testbenches , including checkers, coverage groups, and reference models Design and run self-checking, directed, and randomized tests Maintain the verification environment, including tracking regressions, bugs, and coverage metrics Drive quality … level designs Core skills Strong commercial experience in functional verification , with ownership of verification strategy and planning Expertise in testbench design using frameworks like UVM or OVM Proficiency with SystemVerilog assertions (SVA) Familiarity with multiple programming languages (e.g., C, C++, Python ) Visa sponsorship will be provided for candidates who require. Please note, you must already be living and working in More ❯

ASIC Design Engineer – Cambridge/UK Remote A US-based start-up has recently expanded into the UK and is building a cutting-edge hardware team comprising ASIC Designers, Verification Engineers, and Architects. With a proven and successful leadership team More ❯