10 of 10 Permanent SystemVerilog Jobs in the East of England

Stevenage Are you an experienced FPGA Designer who enjoys contributing to the development of complex FPGA platforms? Look no further! Join our ambitious team at MBDA and be part of a company that is at ...

test) Strong background in Digital Signal Processing (DSP) design and optimisation Excellent academic background with a degree from a top university Proficiency in SystemVerilog or VHDL Proven ability to take technical ownership, collaborate effectively, and deliver complex projects Position: Senior FPGA Engineer Location: Cambridge Salary: £70k–£120k + equity ...

software and infrastructure teams to optimise full-stack performance. Requirements: 7 years FPGA/RTL design experience in timing-critical systems. Strong background in SystemVerilog, synthesis, timing closure and verification. Hands-on with Vivado/Quartus or equivalent toolchains. Familiarity with AXI, PCIe, Ethernet or custom high-speed interfaces. Bonus ...

address varied technical challenges “Nice To Have” Skills And Experience Knowledge of CPU architecture and micro-architecture concepts Experience in RTL Verification & Design techniques (SystemVerilog or VHDL) Experience in software testing and library API design Exposure to dependency management tools, performance profiling techniques In Return At Arm, you’ll join ...

Job Description Join our innovative team as an Analog Integrated Circuit Design Engineer, where you will play a crucial role in designing high speed data converters and PLLs (phase locked loop) specifically for optical communication ...

digital hardware design experience, including 3-5 years in a leadership/management role Strong experience with RTL design (VHDL/Verilog/SystemVerilog), simulation, synthesis, timing analysis, and hardware validation Knowledge of high-speed interfaces, DSP, control logic, and Image Processing Understanding of hardware-software co-design, embedded systems ...

blocks under guidance from senior engineers Contribute to microarchitecture definition by analysing specifications and documenting design decisions Write clean, synthesisable RTL in Verilog or SystemVerilog for small to medium-sized logic blocks Perform basic verification of RTL using simulation tools, including writing simple testbenches and assertions Assist in debugging functional … related field Strong understanding of digital logic design, computer architecture, and basic hardware design principles Familiarity with RTL design using Verilog or SystemVerilog (university, internship, or project experience) Knowledge of hardware description languages, simulation concepts, and basic verification methods Experience with scripting languages such as Python, Tcl, or Bash Familiarity ...

Design Engineer ? Developing complex FPGA architectures and design implementations using VHDL, Simulink, targeting Xilinx, Intel, and Microsemi devices. Verifying FPGA implementations using VHDL and SystemVerilog/UVM test-bench methodologies. Utilizing FPGA design toolsets and Mentor verification tools such as QuestaSim and ModelSim. Writing low-level software … Design Engineer ? Degree-qualified (or equivalent) with significant experience in FPGA development. Strong VHDL language and design skills. Proven verification skills using VHDL and SystemVerilog methodologies. Demonstrable experience designing for Xilinx, Intel, or Microsemi FPGAs. Experience in professionally configuring and documenting designs. Experience working in large, multidiscipline teams. My client ...

equivalent) candidates with significant experience in FPGA development. Proficient in VHDL language and Design Skills. (Highly essential) Proficient in verification skills using VHDL and SystemVerilog methodologies. (Highly essential) Extensive experience designing for Xilinx, Intel, or Microsemi FPGAs. Experience in professional configuration and documentation of designs. Experience working as part ...

software and infrastructure teams to optimise full-stack performance. Requirements: 7+ years FPGA/RTL design experience in timing-critical systems. Strong background in SystemVerilog, synthesis, timing closure and verification. Hands-on with Vivado/Quartus or equivalent toolchains. Familiarity with AXI, PCIe, Ethernet or custom high-speed interfaces. Bonus ...