Design Verification Engineer
City of London, London, United Kingdom
Hybrid/Remote Options
Hybrid/Remote Options
Quest Global
Strong experience with UVM based verification, setting up co-simulation environments with ARM CPU models Job Responsibilities: Work on HVL (UVM/SystemVerilog/OVM), C/C++, Perl, TCL programming/scripting skills, verification methodologies and flows. Perform constraint random verification, assertion writing, coverage analysis, debugging. Work with ARM cores, formal verification, SV DPI-C. Experience with verification tools More ❯
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