1 to 25 of 34 Permanent Tcl Jobs in the UK

FPGA implementation Experience with ASIC flows or FPGA-ASIC migration Familiarity with standards/quality in the aerospace/space domain (e.g. radiation mitigation, reliability) Experience with scripting (Python, Tcl, Bash, etc.) for automation and flow integration Knowledge of formal verification, constraint generation, or static analysis tools Experience working in remote/hybrid settings, distributed teams What We Offer Competitive More ❯

e.g. error correction, equalisation, beamforming, channel estimation) Familiarity with AMBA bus protocols Practical experience with UVM verification methodologies C++/SystemC experience for modelling and integration Scripting skills (Python, Tcl, Bash) for automation and flows Understanding of project methodologies (agile, waterfall, requirements traceability) Experience with AMD/Xilinx FPGAs and/or ASIC backend EDA flows What We Offer Competitive More ❯

of ITIL (nice to have) Experience in an IT support/help desk or SW support environment is preferable 4 years experience with Enovia Knowledge/experience in: MQL, TCL Change process Preferred: Project management, Requirements gathering, Testing. Services advertised by Gold Group are those of an Agency and/or an Employment Business. We will contact you within the More ❯

of ITIL (nice to have) Experience in an IT support/help desk or SW support environment is preferable 4 years experience with Enovia Knowledge/experience in: MQL, TCL Change process Preferred: Project management, Requirements gathering, Testing. Services advertised by Gold Group are those of an Agency and/or an Employment Business. We will contact you within the More ❯

bring-up, and debug of HAPS-based setups Key skills: FPGA firmware development, experience in Interfaces such as SPI, I2C, UART, GPIO, Raspberry Pi, Test automation scripting languages - Python, TCL to 10 years of experience Strong experience in CPLD/FPGA firmware development using Verilog/SystemVerilog Proficiency in scripting languages (e.g., Python, TCL) for automation and debug Hands-on More ❯

a multidisciplinary team to solve complex problems. Stay updated with the latest FPGA technologies and design tools. Required Skills & Qualifications: Extensive experience with VHDL for FPGA development. Proficient with TCL scripting and Modelsim/Questasim. Familiarity with current FPGA and SoC technologies, including Quartus tool chain. Degree or postgraduate degree in a relevant STEM subject. Ability to produce high-quality More ❯

of ITIL (nice to have) Experience in an IT support/help desk or SW support environment is preferable 4 years experience with Enovia Knowledge/experience in: MQL, TCL Change process Preferred: Project management, Requirements gathering, Testing. Services advertised by Gold Group are those of an Agency and/or an Employment Business. We will contact you within the More ❯

design, ideally including work at 7nm or below Practical knowledge of timing closure, clock tree design, physical verification, and sign-off processes Strong scripting/programming ability (e.g. Python, Tcl) Email - jordan.browne@ic-resources.com Tel - 01189073075 LinkedIn - https://www.linkedin.com/in/jordan-browne-b4a08b20b/ More ❯

bring-up, and debug of HAPS-based setups Key skills: FPGA firmware development, experience in Interfaces such as SPI, I2C, UART, GPIO, Raspberry Pi, Test automation scripting languages – Python, TCL to 10 years of experience Strong experience in CPLD/FPGA firmware development using Verilog/SystemVerilog Proficiency in scripting languages (e.g., Python, TCL) for automation and debug Hands-on More ❯

bring-up, and debug of HAPS-based setups Key skills: FPGA firmware development, experience in Interfaces such as SPI, I2C, UART, GPIO, Raspberry Pi, Test automation scripting languages Python, TCL to 10 years of experience Strong experience in CPLD/FPGA firmware development using Verilog/SystemVerilog Proficiency in scripting languages (e.g., Python, TCL) for automation and debug Hands-on More ❯

of ITIL (nice to have) Experience in an IT support/help desk or SW support environment is preferable 4 years experience with Enovia Knowledge/experience in: MQL, TCL Change process Preferred: Project management, Requirements gathering, Testing. Services advertised by Gold Group are those of an Agency and/or an Employment Business. We will contact you within the More ❯

of ITIL (nice to have) Experience in an IT support/help desk or SW support environment is preferable 4 years experience with Enovia Knowledge/experience in: MQL, TCL Change process Preferred: Project management, Requirements gathering, Testing. Services advertised by Gold Group are those of an Agency and/or an Employment Business. We will contact you within the More ❯

analyses) or similar. Additional experience with radio frequency systems, DSP, embedded software and/or requirements management using DOORS would be beneficial. Further experience with C++, VHDL, Python and Tcl would be desirable. Due to the nature of projects, the role is mostly onsite, although occasional home working is possible when projects allow. In return, on offer is a competitive More ❯

and verification, including: Defining functional requirements for verification environments & metrics SystemVerilog UVM testbenches Formal proof verification Understanding of C test cases and C code Scripting languages (e.g. Python, Perl, TCL) Desirable skills Experience with formal verification tools (JasperGold, VC Formal) Familiarity with C/C++ development Prior SSD experience with storage interfaces such as SAS or PCIe (NVMe preferred) What More ❯

timing closure, CDC, RDC, and coverage analysis. Profile Essential Skills Degree in Computer Science, Engineering, or related field. Strong experience with SystemVerilog or VHDL . Competence in scripting (Python, Tcl). Knowledge of digital design flows. Processor design and application-specific blocks. High-speed serial interfaces & complex third-party IP integration. Arithmetic pipeline and floating-point design. Design-for-test More ❯

timing closure, CDC, RDC, and coverage analysis. Profile Essential Skills Degree in Computer Science, Engineering, or related field. Strong experience with SystemVerilog or VHDL . Competence in scripting (Python, Tcl). Knowledge of digital design flows. Processor design and application-specific blocks. High-speed serial interfaces & complex third-party IP integration. Arithmetic pipeline and floating-point design. Design-for-test More ❯

timing closure, CDC, RDC, and coverage analysis. Profile Essential Skills Degree in Computer Science, Engineering, or related field. Strong experience with SystemVerilog or VHDL . Competence in scripting (Python, Tcl). Knowledge of digital design flows. Desirable Experience Processor design and application-specific blocks. High-speed serial interfaces & complex third-party IP integration. Arithmetic pipeline and floating-point design. Design More ❯

power design, high-speed interfaces (e.g., HBM, DDR5, PCIe), and standard on-chip protocols. Experience with microarchitecture exploration, performance modelling, and power optimisation techniques. Scripting ability in Python or TCL to automate design and analysis workflows. This is a superb opportunity to shape next-generation AI hardware from the ground up, working with a passionate team that values innovation, technical More ❯

SystemVerilog Assertions) Testbench design with verification frameworks like UVM/OVM, e, VMM Debugging skills – RTL – Testbench, OOP – Gate level (including SDF) Scripting experience with Ruby, sh/csh, TCL, Make, Perl Power aware verification (using CPF/UPF) This position is based in Edinburgh. This is a hybrid remote position and will follow a 2+ day in-office work More ❯

Design Verification Engineers — Next-Generation AI ASICs Cambridge or Edinburgh An innovative fabless semiconductor start-up is developing cutting-edge AI accelerator chips designed to deliver an order-of-magnitude performance improvement while dramatically reducing power consumption. I am seeking More ❯

design, ideally including work at 7nm or below Practical knowledge of timing closure, clock tree design, physical verification, and sign-off processes Strong scripting/programming ability (e.g. Python, Tcl) Email - jordan.browne@ic-resources.com Tel - 01189073075 LinkedIn - https://www.linkedin.com/in/jordan-browne-b4a08b20b/ More ❯

design, ideally including work at 7nm or below Practical knowledge of timing closure, clock tree design, physical verification, and sign-off processes Strong scripting/programming ability (e.g. Python, Tcl) Email - jordan.browne@ic-resources.com Tel - 01189073075 LinkedIn - https://www.linkedin.com/in/jordan-browne-b4a08b20b/ More ❯

and verification, including: Defining functional requirements for verification environments & metrics SystemVerilog UVM testbenches Formal proof verification Understanding of C test cases and C code Scripting languages (e.g. Python, Perl, TCL) Desirable skills Experience with formal verification tools (JasperGold, VC Formal) Familiarity with C/C++ development Prior SSD experience with storage interfaces such as SAS or PCIe (NVMe preferred) What More ❯

timing closure, CDC, RDC, and coverage analysis. Profile Essential Skills Degree in Computer Science, Engineering, or related field. Strong experience with SystemVerilog or VHDL . Competence in scripting (Python, Tcl). Knowledge of digital design flows. Processor design and application-specific blocks. High-speed serial interfaces & complex third-party IP integration. Arithmetic pipeline and floating-point design. Design-for-test More ❯

timing closure, CDC, RDC, and coverage analysis. Profile Essential Skills Degree in Computer Science, Engineering, or related field. Strong experience with SystemVerilog or VHDL . Competence in scripting (Python, Tcl). Knowledge of digital design flows. Processor design and application-specific blocks. High-speed serial interfaces & complex third-party IP integration. Arithmetic pipeline and floating-point design. Design-for-test More ❯