3 of 3 Cadence Jobs in Central London

experience with RTL design (IP or SoC level). Proficiency in performance optimisation, including power, area, and frequency trade-offs. Hands-on experience with ASIC design tools (e.g., Synopsys, Cadence, etc.). Desirable Experience Understanding of verification methodologies such as UVM or formal verification. Exposure to GPU, CPU, DSP, or FPU architecture and debug/test strategies. Experience with More ❯

micro‐bump/flip‐chip escape routing so 100 + channels meet skew and return‐loss targets. Perform parasitic extraction and EM/IR, thermal and electro‐migration analysis (Cadence Quantus/Calibre xRC, Voltus, EMX/HFSS), iterate with circuit designers to close speed, noise and phase‐noise margins. Optimise critical paths for minimal capacitance and series inductance … production CMOS technologies, with multiple tape‐outs that include > 10 GHz analog front‐ends or 56 ‐ 112 Gb/s SerDes/CDR/PLL blocks. Expert user of Cadence Virtuoso custom layout tools plus sign‐off flows (PVS/Calibre DRC‐LVS, Quantus/StarRC, Voltus/RedHawk). Deep understanding of parasitic‐aware matching, device symmetry, shielding More ❯

clock‐mesh, and micro‐bump/flip‐chip escape routing to meet skew and return‐loss targets. Perform parasitic extraction and EM/IR, thermal, and electro‐migration analysis (Cadence Quantus/Calibre xRC, Voltus, EMX/HFSS), iterating with circuit designers to optimize speed, noise, and phase‐noise margins. Optimize critical paths for minimal capacitance and series inductance … layout in production CMOS technologies, with multiple tape‐outs including >10 GHz analog front‐ends or 56‐112 Gb/s SerDes/CDR/PLL blocks. Expertise in Cadence Virtuoso, sign‐off flows (PVS/Calibre DRC‐LVS, Quantus/StarRC, Voltus/RedHawk). Deep understanding of parasitic‐aware matching, device symmetry, shielding, differential routing, guard‐ring More ❯