1 to 2 of 2 SystemVerilog Jobs in the Thames Valley

/verification involvement Required Skills and Qualifications Metric driven verification - verification planning, requirements extraction - Directed and constrained random verification - Functional and code coverage analysis SystemVerilog Testbench design with verification frameworks like UVM/OVM, e, VMM Debugging skills - RTL - Testbench, OOP - Gate level (including SDF) Formal verification and verification qualification more »

ASIC Verification Engineer – Working on bleeding process nodes and at huge volume with Silicon Valley! Location: Oxfordshire (Hybrid Model) This is an interesting opportunity for an ASIC Verification Engineer to join a leading provider of high-performance client data centre more »