16 of 16 Electronic Design Automation Jobs in the East of England

power, performance and system integration of our products, but we also craft the design flows, influence Electronic Design Automation (EDA) tools and build the knowledge base that makes performant and efficient chip design possible. Our work goes beyond multiple divisions where we drive improved implementation ...

hard-working, creative and motivated engineer to join our GPU development team! We need someone who can work closely with the block design teams, crafting and implementing new processes and methodologies needed to develop next generation GPUs. The successful candidate will be an experienced hardware design engineer with … methodologies to improve GPU power, performance and area (PPA). Required Skills and Experience :Experience with hardware description languages (System Verilog preferable).Experience using EDA simulators (Siemens, Synopsys, Cadence)Strong problem solving and debugging skills, and ability to closely collaborate with other teams. Experience working with version control and code ...

Staff Subsystem Design Engineer Job Overview Arm's IP and Technology team in Solutions Engineering department evelop subsystem solutions and SoC IPs for next-generation systems targeting Edge AI, Physical AI and Cloud AI. We work across Arm, bringing together the latest Arm technologies and selected third-party … complex subsystem and SoC development. Ability to analyse high-level specifications and translate them into efficient and robust microarchitectures. Familiarity with industry-standard EDA tools and methodologies. Experience with static design checks including Lint, CDC, RDC and X-propagation. Experience with synthesis, timing analysis and power-management techniques. Understanding ...

DescriptionObjective of the role: Based in our Cambridge office you will work closely with colleagues locally and in the other IC Design Centres to implement all the digital functions of the mixed signal products developed by Power Integrations. You will work with the Product Definition, IC Design … executing designs via a fully synthesised digital design flow with RTL and logic synthesis. Be fully conversant with the SystemVerilog standard and digital EDA tools. Be familiar with the use of constraints and the automatic place-and-route flow for the physical design. Understand the importance of production test ...

/refactor support).Collaborate with Arm Engineering teams to capture real engineering struggles and turn them into clear requirements. Build quick prototypes and evaluate EDA AI tools, to validate feasibility and quantify impact. Drive adoption as a change leader: run demos/workshops; Contribute onboarding guides; Identify and remove adoption … verification methodology: Deep understanding of RTL design, interfaces between RTL, testbench and Verification IP, experience with debugging compile and simulation issues. Experience with EDA vendor tooling: Domain knowledge of at least one (of the three major) EDA vendor toolset. AI tooling fluency: Practical experience using AI for engineering automation ...

fantastic opportunity has arisen for a Staff Digital IC Design Engineer to join an established Technology company in Cambridge, working on the development of digital functions for mixed-signal products. This role will take responsibility for digital IC design throughout the development lifecycle, from product definition and architecture … design methodologies. Strong experience delivering fully synthesised digital designs through RTL and logic synthesis flows. Experience working with SystemVerilog and industry-standard digital EDA tools. Familiarity with design constraints and automated place-and-route flows. A strong understanding of production test requirements and digital test methodologies. Experience with ...

refactor support). Collaborate with Arm Engineering teams to capture real engineering struggles and turn them into clear requirements. Build quick prototypes and evaluate EDA AI tools, to validate feasibility and quantify impact. Drive adoption as a change leader: run demos/workshops; Contribute onboarding guides; Identify and remove adoption … verification methodology: Deep understanding of RTL design, interfaces between RTL, testbench and Verification IP, experience with debugging compile and simulation issues. Experience with EDA vendor tooling: Domain knowledge of at least one (of the three major) EDA vendor toolset. AI tooling fluency: Practical experience using AI for engineering automation ...

designs, develop UPF files and validate them to ensure robust power management across complex architectures. You will collaborate with multi-functional teams, influence EDA flows and work to optimize power domains, islands and level shifters while supporting partners to achieve high-quality results. #J-18808-Ljbffr ...

processors—including CPUs, GPUs, and neural accelerators and this is where you come in! You will be joining a Fabric IP company as a Design Verification Engineer, contributing your strong background in developing testbenches and writing test sequences for complex IPs. In this role, you will play a pivotal … years and current hands-on experience in block-level/IP-level/SoC-level verification Proficiency in Verilog, SystemVerilog Familiarity with industry-standard EDA tools for simulation and debug Deep experience with UVM-based testbenches Experience with modern programming languages like Python Knowledge of Arm AMBA protocols such ...

Lead Firmware Engineer Basildon 6-Month Contract Paying up to £88p/h (Inside IR35) Key Responsibilities Firmware requirements capture and management. FPGA design and analysis. Production of documentation for other engineers and evidence for design reviews. Development of FPGA test andFPGA integrationplans. Performsystem integrationwork with PCB designers … would be advantageous. Debugging firmware designs and supporting verification and integration at hardware and system level alongside Software and Hardware Engineers Familiarity with Siemens EDA, FPGA development tools, including HDL Designer and ModelSim/Questa, is an advantage. #J-18808-Ljbffr ...

Overview: We are looking for an EDA Optimisation Engineer to support the data-driven optimisation, analysis and maintenance of Arm’s engineering platforms. This role will work as part of a team effort to improve system utilisation/efficiency/cost-performance and touch on forecasting accuracy and infrastructure strategy. … finance teams to ensure data-driven decision making. Required Skills and Experience : Background in distributed HPC, cloud environments, data engineering & analytics. Knowledge of EDA workflows and semiconductor engineering environments. Proficiency in Python and data analysis/ML frameworks. Ability to turn sophisticated data into clear, actionable strategy. “Nice To Have ...

will have proven experience in delivering industry‐leading verification quality and productivity under tight schedules. In this role the candidate will collaborate with architecture, design and central formal verification teams to define our formal verification roadmap, strategy, methodology, infrastructure and expand formal verification adoption through project execution. The candidate … engines and use cases Proven expertise in system Verilog assertion and abstract model development Expert user of formal verification tools from both academia and EDA vendors (JasperGold, VC formal, Murphi, theorem prover) Proven track record of delivering high quality verification under tight schedule for modern, large‐scale processor design ...

next-generation compute architectures, developing high-performance, power-efficient CPU technology on the most advanced process nodes, is looking for an experienced Physical Design Engineer to join its growing team. You will play a key role in the implementation of cutting-edge CPU IP within a world-class engineering …/SoC designs Experience across the full implementation flow including floorplanning, place and route, CTS and physical sign-off Familiarity with industry-standard EDA tools such as Innovus, ICC2, Fusion Compiler or equivalent Good understanding of timing closure, power optimisation and physical verification methodologies Strong scripting skills with TCL, Python ...

formal verification methodology to achieve industry leading verification quality and productivity under tight schedule. In this role the candidate will work with architecture team, design team and central formal verification team to define our formal verification roadmap, strategy, methodology, infrastructure and expand formal verification adoption through project execution. … verification algorithms, engines and use casesProven expertise in system Verilog assertion and abstract model developmentExpert user of formal verification tools from both academy and EDA vendors (JasperGold, VC formal, Murphi, theorem prover)Proven track record of delivering high quality verification under tight schedule for modern, large scale processor design ...

Limited in Cambridge is seeking an EDA Optimisation Engineer to drive data-driven optimisation, analysis and maintenance of Arm’s engineering platforms. You will help improve system utilisation, efficiency and cost-performance across HPC compute, cloud, Emulation and FPGA environments. In a metrics-first environment, you will develop dashboards, pipelines ...

Accelerator grant to develop solutions for frontier applications of integrated photonics. Today we are a team of around 20 people in Cambridge, automating PDK design for integrated photonics and building the hub that connects chip designers, IP providers and foundries. Behind the product sits a serious compute and data …/Beneficial HPC‐style job scheduling (Kueue, Slurm, MPI, or similar). Experience with large scientific or array datasets. Any background in photonics, semiconductors, EDA, or scientific computing. We are particularly interested in people who can solve complex problems, learn quickly and make a meaningful contribution. ...