7 of 7 Verification Engineer Jobs in the East of England

seeking a Senior Verification Engineer to join a rapidly growing HW Team in Cambridge. You will get the opportunity to work on cutting edge technology and in the area of quantum computing. No prior experience in quantum computing? No problem. You'll learn as you go while working … alongside world-class engineers in a truly cross-disciplinary environment. As a Senior Verification Engineer, you will take ownership of verification across block, subsystem, and multi-FPGA system-level designs. With visibility across the entire stack, you will partner closely with the Lead Verification Engineer ...

make fault-tolerant quantum computing a reality. We're making remarkable progress and growing fast. About the roleWe have an exceptional opportunity for a Verification/Senior Verification Engineer to join our talented team of hardware designers and embedded software engineers. Together, you'll deliver fully verified … high-performance, and trusted systems. In this exciting role you'll have end-to-end visibility across the entire stack, owning every aspect of verification and shaping how quality and reliability are built into our cutting-edge technology. You do not need a background in quantum computing! You will ...

Exciting opportunity for a Lead Verification Engineer to help establish a new European engineering team, bringing existing DV colleagues or building a team from the ground up within the RISC-V and open-source silicon space. Build a New European Digital Verification Team - Permanent Opportunity The Opportunity … source silicon, secure hardware and processor IP, with strong links to the lowRISC ecosystem. The business is looking to establish a new European Digital Verification function and is seeking an experienced Lead Verification Engineer to play a key role in building the team, driving technical direction ...

Overview: This is a great opportunity for an experienced and highly motivated Staff Engineer to join Arm's CPU team in Cambridge. The role involves working on the next generation of CPU products. You will build and refine simulation-focused verification environments for future CPU IP, working … close collaboration with design and verification teams. You will be able to affect both design and verification decisions and assist in shaping technology used in billions of devices worldwide. As CPU designs become increasingly complex, robust and efficient verification is essential to delivering high-quality products. ...

Title - Senior SoC Design Verification Engineer Location: Cambridge/Bristol UK, Employment Type: Contract (Inside Ir35). Role Overview We are looking for experienced SoC Design Verification (DV) Engineers to work on the verification of a next-generation, multi-die System-on-Chip (SoC) design. Engineers … will be responsible for subsystem-level and SoC-level functional verification using System Verilog/UVM methodology, as well as processor-driven verification using C-based test programs executing on Embedded processor cores. The role requires strong debugging and analytical skills, an understanding of ARM processor based ...

Overview: In the fast-evolving world of CPU verification, formal methods are playing an increasingly vital role in enabling rapid, innovative development. Arm's CPU Group is seeking experienced formal verification engineers who are excited to apply modern techniques and push the boundaries of what formal verification can achieve on groundbreaking designs. This is an outstanding opportunity to join a passionate, dedicated team deploying formal verification on the next generation of CPU designs. You'll have the chance to influence both design and verification decisions, helping to shape technology that will power billions ...

What if your next verification role gave you the opportunity to work on silicon technology that's helping shape the future of open-source hardware? I am looking to speak with talented Digital Verification Engineers with 35 years' experience who are ready to take on new technical challenges … years' industry experience in Digital Design Verification. Strong hands-on SystemVerilog and UVM experience. Experience developing and debugging UVM testbenches. Some exposure to Formal Verification . Understanding of verification planning, functional coverage and regression testing. Python and/or C programming experience. What's on offer? Permanent position ...