10 of 10 ASIC Jobs in the City of London

FPGA/ASIC Design: My client is a renowned HPC research-led hardware team that values true engineering expertise and places great emphasis on problem-solving, critical thought, and versatility. The FPGA team collaborates closely with traders and software engineers to identify key challenges and develop effective solutions to issues that occur in sub microsecond trading. At their core, my More ❯

and industry-standard methodologies. Proven experience with RTL design (IP or SoC level). Proficiency in performance optimisation, including power, area, and frequency trade-offs. Hands-on experience with ASIC design tools (e.g., Synopsys, Cadence, etc.). Desirable Experience Understanding of verification methodologies such as UVM or formal verification. Exposure to GPU, CPU, DSP, or FPU architecture and debug/ More ❯

A skilled communicator and collaborator, you thrive in a fast-paced, innovative environment. Required Skills: Expertise in digital IC design and RTL at IP or SoC level. Proficiency in ASIC/FPGA design tools and optimization techniques. Strong analytical and problem-solving abilities. Preferred Skills: Experience with verification methodologies (UVM, assertions, formal verification). Knowledge of CPU/GPU/ More ❯

us in London to be part of a highly motivated and skilled team that thrives on delivering impact and innovation at speed. The role We’re searching for a ASIC Lead (Digital) who can drive a complex, high‐speed mixed‐signal chip from concept to mass production while line‐managing and mentoring a world‐class team of design engineers. You … serve as the principal technical authority for every digital block that underpins our OTPU. Responsibilities Architect, plan and deliver the digital top level of a multi‐lane optical compute ASIC—RTL, synthesis, DFT/DFD, static‐timing and physical implementation. Lead cross‐functional teams (digital, analog, verification, layout, packaging, test, firmware) through all silicon lifecycle stages: architecture ► spec ► RTL ► physical … monitoring, calibration engines and field‐update hooks. Encourage a culture of continuous improvement —methodology automation, design‐flow enhancements, documentation and knowledge sharing. Skills & Experience 12 + years of digital ASIC development, with at least 3 full product cycles taken from specification through volume production. Demonstrated success leading a digital team that delivered high speed ASICs containing high‐speed mixed‐signal More ❯

in Verilog/SystemVerilog Developing high-speed modules (PCIe, Ethernet, DDR/QDR) with deep pipelining Using simulation and formal tools (Verilator, Cocotb, etc.) for validation Working across teams (ASIC, software, infra) to co-design tightly coupled platforms Contributing to tooling, flow, and potentially DSL extensions (OCaml or similar) What We’re Looking For Strong RTL skills with experience building More ❯

formal verification, emulation, coverage‐driven flows, RISC‐V vectors, and AI‐centric design techniques to keep Flux at the forefront of silicon quality. Skills & Experience 3+ years in digital ASIC/SoC design & verification, with at least two tape‐outs. Mastery of SystemVerilog/UVM, functional coverage, constraint‐random stimulus and scoreboards. Deep understanding of clock‐domain crossing, reset and More ❯

ASIC Design Engineer London/Remote Experience Level: 3–5 years I am looking for a talented and motivated Hardware Design Engineer to join a UK based HW team. They are a leading global provider of high-performance IP and custom silicon solutions; this company is recognized for its deep expertise in advanced process technologies and interface IP. You will … Solid understanding of digital design principles, including pipelining, clock domain crossing, and low-power design techniques, high performance design techs. Proficient in Verilog/SystemVerilog/VHDL. Familiar with ASIC design flow and tools. Experience with GPU design or computer graphics architecture. Familiarity with high-speed interfaces and memory subsystems. Familiarity with modern graphics. You must have full UK working More ❯

linting + Complete projects from conception to completion Skills Required: + Experience with frontend RTL Design + Strong Experience with SystemVerilog, Verilog or VHDL + Has had exposure to ASIC design flow (Lint, syntheisis, simulation) + Digital Design Principles experience pipelining, clock domain crossing Further Details: This role offers remote working with a potential visit into the office every month. More ❯

Key Responsibilities: Collaborate with a team of FPGA hardware and software engineers to develop and scale ultra-low latency trading systems. Shape the technology roadmap and lead FPGA/ASIC projects from inception to completion. Drive the creation of productivity tools and enhance RTL design workflows. Keep up to date with the latest developments in hardware and open-source FPGA … a specialist in FPGA engineering. Qualifications: Bachelor’s or Master’s degree in Electrical Engineering, Computer Science, or a related field. Minimum of 5 years’ experience in FPGA/ASIC design engineering. Strong knowledge of networking protocols, including Ethernet/IP/TCP/UDP. Familiarity with Linux environments. Why Join Us? Work in a fast-paced, collaborative environment in More ❯

to be part of a highly motivated and skilled team that thrives on delivering impact and innovation at speed. The role We’re searching for a Director of Hardware - ASIC to own the technical, schedule and organisational delivery of multiple ASICs within OTPU. You will line‐manage the Analog ASIC Lead and Digital ASIC Lead (each with their own teams … Success demands a rare blend of hands‐on technical depth, proven people leadership and disciplined program management—all exercised across multiple concurrent tape‐outs. Responsibilities Build and maintain the ASIC master schedule—including IP development, verification, physical implementation, package co‐design, MPW/test‐chip shuttles, qualification and production ramps. Drive weekly cross‐functional reviews and executive read‐outs. Directly … manage and mentor the Analog and Digital ASIC Leads (and, via them, ~25 + engineers). Set goals, hire strategically, grow technical leaders and foster a culture of first‐pass silicon success. Provide architectural guidance and critical design‐review sign‐off for blocks running from > 20 GHz analog bandwidth to > 100 MHz digital core clocks . Resolve spec splits, timing More ❯