Design Verification Engineer
- Hiring Organisation
- Platform Recruitment
- Location
- London Area, United Kingdom
Python for building verification infrastructure, tooling, and automation - beyond simple scripts. At least two years of professional RTL functional verification experience for FPGA or ASIC designs. Hands-on expertise in SystemVerilog and UVM, including stimulus development and code/functional coverage collection and analysis. Experience with cocotb desirable. Apply below ...