3 of 3 ASIC Jobs in Peterborough

floorplanning, CTS, place-and-route and sign-off, plus scripting in TCL, Python, or Perl to enhance flows and automation. A strong background in ASIC/CPU/SoC physical design is essential. #J-18808-Ljbffr ...

genuine impact on product development. The successful STA Engineer will have experience in: Performing full-chip and block-level static timing analysis on complex ASIC and SoC designs. Driving timing closure across all implementation stages, from synthesis through to sign-off. Analysing and resolving setup, hold, clock gating and signal … nodes. Requirements: A strong academic background in Electronics, Electrical Engineering or a related discipline. Proven industry experience in Static Timing Analysis, Physical Design or ASIC implementation. Deep understanding of timing closure methodologies and sign-off flows for advanced ASIC and SoC designs. Strong knowledge of industry-standard EDA tools such ...

small, collaborative team, allowing broad impact on performance, power and area, plus opportunities to own timing closure and support sign-off activities across advanced ASIC/SoC projects. #J-18808-Ljbffr ...