1 to 25 of 75 ASIC Jobs in the UK

/as a chip lead/or SOC architect Digital/AMS, analog-mixed-signal IP End to end chip/SOC delivery experience ASIC & FPGA - verilog, system verilog, VHDL ADC/DAC - digital - analog interfaces Functional verification - system verilog - IP, system, sub-system, block, top level experience Creation ...

based start-up has recently expanded into the UK and is building a cutting-edge hardware team comprising ASIC Designers, Verification Engineers, and Architects. With a proven and successful leadership team, this company offers a unique opportunity to be part of the AI revolution from the ground up. ...

based start-up has recently expanded into the UK and is building a cutting-edge hardware team comprising ASIC Designers, Verification Engineers, and Architects. With a proven and successful leadership team, this company offers a unique opportunity to be part of the AI revolution from the ground up. ...

understand how and why it works) Proven experience in high-level modelling and simulation of complex systems Strong understanding of mixed-signal systems, ASIC design concepts, and analysis tools Proficiency with MATLAB, Simulink and/or Python (two or more required) Experience using version control systems like Git or Subversion ...

ASIC Architect Location: Remote Key Responsibilities ASIC strategy & architecture Assess system components to determine which should be implemented as ASIC versus FPGA or GPU. Define ASIC architecture in alignment with overall system requirements, including interfaces and memory hierarchy. Evaluate trade-offs between different processing units (ASIC, FPGA … chip/die-to-die interfaces. Drive top-level floorplanning. Direct functional simulations and co-simulation across multiple domains. Design & development Oversee the ASIC design lifecycle: specification, RTL design, verification, and physical implementation. Ensure compatibility with system-level interfaces and integration requirements. Fabrication & packaging Manage relationships with semiconductor foundries ...

/Satellite experience (Phases B, C, D). OBC (On-Board Computer), MMFU (Mass Memory), and RIU (Remote Interface Unit). Hardware: FPGA/ASIC design. Communication Protocols: SpaceWire , MIL-STD-1553 , or CAN bus . Master's degree in electrical engineering or a comparable field such as physics ...

chip team to support a major US tech programme. They're looking for experienced Digital Verification Engineers to work on advanced ASIC Core/IP development. Fully remote across the UK with quarterly visits to London. What You'll Do Own unit‐level and core‐level verification for complex digital ...

chip team to support a major US tech programme. They're looking for experienced Digital Verification Engineers to work on advanced ASIC Core/IP development. Fully remote across the UK with quarterly visits to London. What You'll Do Own unit‐level and core‐level verification for complex digital ...

teams and programming languages to find root causes of deep and complex issues Experience of the verification process applied in CPU and/or ASIC environments System Verilog, Python, C++, Linux UVM SVA LLVM, GCC SGE or other DRMS XML and XPath/XSLT Benefits In addition to a competitive ...

teams and programming languages to find root causes of deep and complex issues Experience of the verification process applied in CPU and/or ASIC environments System Verilog, Python, C++, Linux UVM SVA LLVM, GCC SGE or other DRMS XML and XPath/XSLT Benefits In addition to a competitive ...

related field 10+ years of experience in industry - delivering IP and/or chips for mass production Good understanding of digital design flows - across ASIC & FPGA Good understanding of analog/mixed-signal environments Deep understanding of SerDes system architecture Good customer facing ability - internally and externally Design specifications ...

related field 10+ years of experience in industry - delivering IP and/or chips for mass production Good understanding of digital design flows - across ASIC & FPGA Good understanding of analog/mixed-signal environments Deep understanding of SerDes system architecture Good customer facing ability - internally and externally Design specifications ...

able to isolate and resolve complex RTL and testbench issues efficiently. At least two years of professional RTL functional verification experience for FPGA or ASIC designs. Hands-on expertise in SystemVerilog and UVM, including stimulus development and code/functional coverage collection and analysis. Proficiency in Python and/ ...

able to isolate and resolve complex RTL and testbench issues efficiently. At least two years of professional RTL functional verification experience for FPGA or ASIC designs. Hands-on expertise in SystemVerilog and UVM, including stimulus development and code/functional coverage collection and analysis. Proficiency in Python and/ ...

software and hardware projects from inception to completion Develop and maintain project schedules, budgets, and resource allocations Collaborate closely with cross-functional teams including ASIC designers and hardware engineers Serve as the primary point of contact for customers throughout the project lifecycle Engage with customers to understand requirements and provide ...

Collaborate closely with RTL design, architecture, and dynamic verification teams across global sites Required Experience & Skills 3–10 years’ experience in Formal Verification within ASIC, SoC, or GPU-adjacent environments Strong hands-on experience with industry-standard formal verification tools Proven expertise writing and debugging SystemVerilog Assertions (SVA) Experience achieving ...

design bugs Experience 5+ years’ experience in the semiconductor industry Proven track record in verifying complex designs (preferably in high volume applications) - FPGA or ASIC Familiarity with SerDes and high-level protocols (e.g., PCle, USB, DP) would be advantageous Extensive digital verification background with some UVM experience. What ...

Regulation (SFTR Reporting) North American Regulations: CFTC (Part 43/45) Securities Based Swap Dealer Reporting (SEC 901/902) APAC Regulations: MAS HKMA ASIC Responsibilities Implementing the Business Requirements for BAU and large projects Securities Based Swap Dealer Reporting (SEC 901/902) Design and development of regulatory reporting ...

Digital Electronics or Avionics . Data Protocols: Expert knowledge of SpaceWire, MIL-STD-1553, and CAN bus . Hardware Logic: Familiarity with FPGA/ASIC design and radiation-hardened electronics. Lifecycle: Experience with ESA/Industry standard mission phases and AIT (Assembly, Integration, and Test) support. Communication: Ability to work ...

compute APIs, such as Vulkan, D3D12 and OpenCL, CUDA etc. Definition of high-level GPU architecture/micro-architecture Confidence knowledge in the ASIC digital design flow Experience in R&D of the latest products and features Ability to take a concept through to production and delivery/tape ...

compute APIs, such as Vulkan, D3D12 and OpenCL, CUDA etc. Definition of high-level GPU architecture/micro-architecture Confidence knowledge in the ASIC digital design flow Experience in R&D of the latest products and features Ability to take a concept through to production and delivery/tape ...

compute APIs, such as Vulkan, D3D12 and OpenCL, CUDA etc. Definition of high-level GPU architecture/micro-architecture Confidence knowledge in the ASIC digital design flow Experience in R&D of the latest products and features Ability to take a concept through to production and delivery/tape ...

compute APIs, such as Vulkan, D3D12 and OpenCL, CUDA etc. Definition of high-level GPU architecture/micro-architecture Confidence knowledge in the ASIC digital design flow Experience in R&D of the latest products and features Ability to take a concept through to production and delivery/tape ...

compute APIs, such as Vulkan, D3D12 and OpenCL, CUDA etc. Definition of high-level GPU architecture/micro-architecture Confidence knowledge in the ASIC digital design flow Experience in R&D of the latest products and features Ability to take a concept through to production and delivery/tape ...

compute APIs, such as Vulkan, D3D12 and OpenCL, CUDA etc. Definition of high-level GPU architecture/micro-architecture Confidence knowledge in the ASIC digital design flow Experience in R&D of the latest products and features Ability to take a concept through to production and delivery/tape ...