in an FPGA development team Desirable: Experience of digital hardware design for FPGA using VHDL Experience and knowledge of video processing and control law algorithms Working knowledge and experience of UVM (Universal Verification Methodology) constrained random verification Benefits: You'll receive benefits including a competitive pension scheme, enhanced annual leave More ❯
in an FPGA development team Desirable: Experience of digital hardware design for FPGA using VHDL Experience and knowledge of video processing and control law algorithms Working knowledge and experience of UVM (Universal Verification Methodology) constrained random verification This really is a fantastic opportunity for an FPGA Engineer to progress their More ❯
VHDL, synthesis, simulation, and verification tools Solid grasp of design constraints and system integration Bonus if you bring: Experience with video processing or control algorithms Knowledge of UVM and constrained-random verification Background in safety-critical or high-integrity systems Disclaimer: This vacancy is being advertised by either Advanced Resource More ❯
