Verification / Senior Verification Engineer
- Hiring Organisation
- Riverlane
- Location
- Cambridge, Cambridgeshire, UK
- Employment Type
- Full-time
testbench design with verification frameworks like UVM/OVM. Knowledge of SystemVerilog assertion (SVA). Exposure to different programming languages, such as C, C++ and Python. A proactive person who can independently define the scope of work. A collaborative person with excellent communication skills, who actively shares (and listens ...