1 to 25 of 28 Cadence Jobs in London

a plus, not a must Understanding of pipelining, memory hierarchies, or parallel compute concepts Interest in learning physical design fundamentals (timing, DFT, floorplanning) Experience using EDA tools (e.g., Synopsys, Cadence, or similar) during academic or internship projects Scripting knowledge in Python, TCL, or equivalent languages BS or MS in Electrical Engineering, Computer Engineering, or a related discipline Verification Requirements More ❯

RISC-V instruction set architecture (preferred) Understanding of graphics pipelines and/or neural network accelerators Awareness of physical design implications (DFT, timing, floorplanning) Proficiency with EDA tools (Synopsys, Cadence, Mentor, etc.) Strong scripting skills in Python, TCL, or similar BS/MS in Electrical Engineering, Computer Engineering, or related field Verification Requirements: 5+ years of experience in hardware More ❯

experience with RTL design (IP or SoC level). Proficiency in performance optimisation, including power, area, and frequency trade-offs. Hands-on experience with ASIC design tools (e.g., Synopsys, Cadence, etc.). Desirable Experience Understanding of verification methodologies such as UVM or formal verification. Exposure to GPU, CPU, DSP, or FPU architecture and debug/test strategies. Experience with More ❯

experience with RTL design (IP or SoC level). Proficiency in performance optimisation, including power, area, and frequency trade-offs. Hands-on experience with ASIC design tools (e.g., Synopsys, Cadence, etc.). Desirable Experience Understanding of verification methodologies such as UVM or formal verification. Exposure to GPU, CPU, DSP, or FPU architecture and debug/test strategies. Experience with More ❯

experience with RTL design (IP or SoC level). Proficiency in performance optimisation, including power, area, and frequency trade-offs. Hands-on experience with ASIC design tools (e.g., Synopsys, Cadence, etc.). Desirable Experience Understanding of verification methodologies such as UVM or formal verification. Exposure to GPU, CPU, DSP, or FPU architecture and debug/test strategies. Experience with More ❯

experience with RTL design (IP or SoC level). Proficiency in performance optimisation, including power, area, and frequency trade-offs. Hands-on experience with ASIC design tools (e.g., Synopsys, Cadence, etc.). Desirable Experience Understanding of verification methodologies such as UVM or formal verification. Exposure to GPU, CPU, DSP, or FPU architecture and debug/test strategies. Experience with More ❯

Our founders are internationally renowned researchers from UCL and Oxford University who have pioneered the development of qubits and quantum computing architectures. Our chairman is the co-founder of Cadence and Synopsys, the two leading companies in the area of Electronic Design Automation. We're backed by a team of top-tier investors including Bosch Ventures, Porsche SE, Sony More ❯

Our founders are internationally renowned researchers from UCL and Oxford University who have pioneered the development of qubits and quantum computing architectures. Our chairman is the co-founder of Cadence and Synopsys, the two leading companies in the area of Electronic Design Automation. We’re backed by a team of top-tier investors including Bosch Ventures, Porsche SE, Sony More ❯

to help others. Preferred Additional Experience, Knowledge, Skills, And Abilities An understanding and experience of design of products aligned with CommTech’s portfolio Experience with Altium Designer Experience with Cadence AWR Microwave Office Experience with Ansys HFSS Electronics experience of switch-mode PSUs, embedded circuitry, glue logic, analogue electronics and EMC circuitry. The following skills and experience would also More ❯

Our founders are internationally renowned researchers from UCL and Oxford University who have pioneered the development of qubits and quantum computing architectures. Our chairman is the co-founder of Cadence and Synopsys, the two leading companies in the area of Electronic Design Automation. We're backed by a team of top-tier investors including Bosch Ventures, Porsche SE, Sony … and at least 5+ years of work experience in RF IC Circuit Design Demonstrated experience in circuit design on or below CMOS 40nm RF processes. Demonstrated experience with the Cadence Design environment and SpectreRF. Solid understanding of the fundamentals of RF design. Capable of providing feedback on the validity of the working principles of a circuit without the assistance More ❯

Our founders are internationally renowned researchers from UCL and Oxford University who have pioneered the development of qubits and quantum computing architectures. Our chairman is the co-founder of Cadence and Synopsys, the two leading companies in the area of Electronic Design Automation. We’re backed by a team of top-tier investors including Bosch Ventures, Porsche SE, Sony … and at least 5+ years of work experience in RF IC Circuit Design Demonstrated experience in circuit design on or below CMOS 40nm RF processes. Demonstrated experience with the Cadence Design environment and SpectreRF. Solid understanding of the fundamentals of RF design. Capable of providing feedback on the validity of the working principles of a circuit without the assistance More ❯

layout vs. schematic (LVS), and other physical verification compliance. Collaborate with DFT engineers to integrate design-for-test (DFT) structures into the physical implementation. Utilise EDA tools such as Cadence Innovus, Synopsys ICC2, Mentor Graphics Calibre, and others. Interface with foundries and process engineers to ensure manufacturability and yield optimisation. Work closely with RTL and architecture teams to drive More ❯

Our founders are internationally renowned researchers from UCL and Oxford University who have pioneered the development of qubits and quantum computing architectures. Our chairman is the co-founder of Cadence and Synopsys, the two leading companies in the area of Electronic Design Automation. We’re backed by a team of top-tier investors including Bosch Ventures, Porsche SE, Sony More ❯

Our founders are internationally renowned researchers from UCL and Oxford University who have pioneered the development of qubits and quantum computing architectures. Our chairman is the co-founder of Cadence and Synopsys, the two leading companies in the area of Electronic Design Automation. We’re backed by a team of top-tier investors including Bosch Ventures, Porsche SE, Sony More ❯

Deep knowledge of track‐and‐hold linearity, aperture‐jitter minimisation, current‐steering DAC glitch energy reduction, capacitor and device matching, and metastability‐hard comparators. Proficiency with industry EDA flows: Cadence Virtuoso, SpectreRF/AFS RF, Verilog‐A/AMS, EMX/HFSS for package + on‐chip inductor modelling, and mixed‐signal verification. Demonstrated ability to achieve Experience incorporating More ❯

micro‐bump/flip‐chip escape routing so 100 + channels meet skew and return‐loss targets. Perform parasitic extraction and EM/IR, thermal and electro‐migration analysis (Cadence Quantus/Calibre xRC, Voltus, EMX/HFSS), iterate with circuit designers to close speed, noise and phase‐noise margins. Optimise critical paths for minimal capacitance and series inductance … production CMOS technologies, with multiple tape‐outs that include > 10 GHz analog front‐ends or 56 ‐ 112 Gb/s SerDes/CDR/PLL blocks. Expert user of Cadence Virtuoso custom layout tools plus sign‐off flows (PVS/Calibre DRC‐LVS, Quantus/StarRC, Voltus/RedHawk). Deep understanding of parasitic‐aware matching, device symmetry, shielding More ❯

micro‐bump/flip‐chip escape routing so 100 + channels meet skew and return‐loss targets. Perform parasitic extraction and EM/IR, thermal and electro‐migration analysis (Cadence Quantus/Calibre xRC, Voltus, EMX/HFSS), iterate with circuit designers to close speed, noise and phase‐noise margins. Optimise critical paths for minimal capacitance and series inductance … production CMOS technologies, with multiple tape‐outs that include > 10 GHz analog front‐ends or 56 ‐ 112 Gb/s SerDes/CDR/PLL blocks. Expert user of Cadence Virtuoso custom layout tools plus sign‐off flows (PVS/Calibre DRC‐LVS, Quantus/StarRC, Voltus/RedHawk). Deep understanding of parasitic‐aware matching, device symmetry, shielding More ❯

micro‐bump/flip‐chip escape routing so 100 + channels meet skew and return‐loss targets. Perform parasitic extraction and EM/IR, thermal and electro‐migration analysis (Cadence Quantus/Calibre xRC, Voltus, EMX/HFSS), iterate with circuit designers to close speed, noise and phase‐noise margins. Optimise critical paths for minimal capacitance and series inductance … production CMOS technologies, with multiple tape‐outs that include > 10 GHz analog front‐ends or 56 ‐ 112 Gb/s SerDes/CDR/PLL blocks. Expert user of Cadence Virtuoso custom layout tools plus sign‐off flows (PVS/Calibre DRC‐LVS, Quantus/StarRC, Voltus/RedHawk). Deep understanding of parasitic‐aware matching, device symmetry, shielding More ❯

micro‐bump/flip‐chip escape routing so 100 + channels meet skew and return‐loss targets. Perform parasitic extraction and EM/IR, thermal and electro‐migration analysis (Cadence Quantus/Calibre xRC, Voltus, EMX/HFSS), iterate with circuit designers to close speed, noise and phase‐noise margins. Optimise critical paths for minimal capacitance and series inductance … production CMOS technologies, with multiple tape‐outs that include > 10 GHz analog front‐ends or 56 ‐ 112 Gb/s SerDes/CDR/PLL blocks. Expert user of Cadence Virtuoso custom layout tools plus sign‐off flows (PVS/Calibre DRC‐LVS, Quantus/StarRC, Voltus/RedHawk). Deep understanding of parasitic‐aware matching, device symmetry, shielding More ❯

micro‐bump/flip‐chip escape routing so 100 + channels meet skew and return‐loss targets. Perform parasitic extraction and EM/IR, thermal and electro‐migration analysis (Cadence Quantus/Calibre xRC, Voltus, EMX/HFSS), iterate with circuit designers to close speed, noise and phase‐noise margins. Optimise critical paths for minimal capacitance and series inductance … production CMOS technologies, with multiple tape‐outs that include > 10 GHz analog front‐ends or 56 ‐ 112 Gb/s SerDes/CDR/PLL blocks. Expert user of Cadence Virtuoso custom layout tools plus sign‐off flows (PVS/Calibre DRC‐LVS, Quantus/StarRC, Voltus/RedHawk). Deep understanding of parasitic‐aware matching, device symmetry, shielding More ❯

and micro‐bump/flip‐chip escape routing so 100+ channels meet skew and return‐loss targets. Perform parasitic extraction and EM/IR, thermal and electro‐migration analysis (Cadence Quantus/Calibre xRC, Voltus, EMX/HFSS), iterate with circuit designers to close speed, noise and phase‐noise margins. Optimise critical paths for minimal capacitance and series inductance … layout in production CMOS technologies, with multiple tape‐outs that include >10GHz analog front‐ends or 56‐112Gb/s SerDes/CDR/PLL blocks. Expert user of Cadence Virtuoso custom layout tools plus sign‐off flows (PVS/Calibre DRC‐LVS, Quantus/StarRC, Voltus/RedHawk). Deep understanding of parasitic‐aware matching, device symmetry, shielding More ❯

Support silicon validation & debugging What You Bring: Proven expertise in Analog IC design (data converters, power management, sensor interfaces) Strong background in transistor-level design, simulation & verification Experience with Cadence tools, CMOS process flows & post-layout PEX Knowledge of Python, Verilog-A, SystemVerilog, MATLAB Passion for design automation and pushing boundaries in semiconductor innovation Why Join? Game-changing technology More ❯

Office e.g., facility issues, lockers, ad hoc issues, stationery orders and Purchasing Card payments Meeting management i.e., draft and manage agenda’s/actions/minutes/meeting governance & cadence for the VP office. Oversee the coordination, planning and execution of the Monthly Townhall meetings Be the business partner to our Facilities partners managing the floor plan/desk More ❯

some or all of the following; PA (power amplifiers), LNAs, Mixers Filters, Phase Shifter, DACs, bandgaps, LDOs and switches A strong knowledge on IC design CAD tools such as Cadence Virtuoso (Spectre RF Experience in the use of LAB RF measurement equipment (Spectrum Analysers, Signal Generators, VNAs) Excellent communication skills in English You will ideally be required to be More ❯

areas of risk ownership ensuring closures are tracked and presented to required stakeholders. Lead and manage the internal review work to achieve efficiency, effectiveness, and timeliness. Establish governance and cadence as enforced per guidelines. Ensure assigned education sessions are conducted in a timely manner. Qualifications: 10 to 15 years of experience working in risk and compliance management, internal security More ❯